Cypress SL811HS - Manuals

Cypress SL811HS – Manual in PDF format online.

Manuals:

Manual

Manual Cypress SL811HS

Summary

Page 2 - Auto Address Increment Mode; Auto Address Increment Example.

SL811HS Document 38-08008 Rev. *D Page 2 of 32 Data Port, Microprocessor Interface The SL811HS microprocessor interface provides an 8-bitbidirectional data path along with appropriate control lines tointerface to external processors or controllers. ProgrammedI/O or memory mapped I/O designs are supp...

Page 3 - PLL Clock Generator; Figure 2; USB Transceiver; on page 4; Figure 2. Full Speed 48 MHz Crystal Circuit; Figure 3. Optional 12 MHz Crystal Circuit

SL811HS Document 38-08008 Rev. *D Page 3 of 32 PLL Clock Generator Either a 12 MHz or a 48 MHz external crystal is used with theSL811HS [1] . Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device as shown in Figure 2 and Figure 3 . Use an external clock source if avai...

Page 4 - Register Name; SL811HS Host Control Registers

SL811HS Document 38-08008 Rev. *D Page 4 of 32 “SL811HS Slave Mode Registers” on page 12 describes Slave register definitions). Access to the registers are through themicroprocessor interface similar to normal RAM accesses(see “Bus Interface Timing Requirements” on page 26 ) and provide control and ...

Page 7 - SL811HS Control Registers; Table 10. SL811HS Control Registers Summary

SL811HS Document 38-08008 Rev. *D Page 7 of 32 USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining(from Host Ba...

Page 8 - Function

SL811HS Document 38-08008 Rev. *D Page 8 of 32 Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined as follows. At powe -up this register is cleared to all zeros. Low-power Modes [Bit 6 Control Register, Address 05h] When bit 6 ...

Page 12 - Endpoint Register Set

SL811HS Document 38-08008 Rev. *D Page 12 of 32 SL811HS Slave Mode Registers When in slave mode, the registers in the SL811HS are dividedinto two major groups. The first group contains Endpoint reg-isters that manage USB control transactions and data flow.The second group contains the USB Registers ...

Page 13 - Endpoint Control Registers; Bit Position

SL811HS Document 38-08008 Rev. *D Page 13 of 32 Endpoint Control Registers Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Each endpoint set has a Control register defined as follows: Endpoint Base Address [Address a = (EP# * 10h)+1, b = (EP# * 10h)+9]]. Pointer to memory b...

Page 14 - USB Control Registers

SL811HS Document 38-08008 Rev. *D Page 14 of 32 Endpoint Packet Status [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]. The packet status contains information relative to the packet that is received or transmitted. The register is defined as follows: Endpoint Transfer Count [Address a = (EP# * 10h)+...

Page 16 - Interrupt

SL811HS Document 38-08008 Rev. *D Page 16 of 32 Interrupt Enable Register, Address [06h] . The SL811HS provides an Interrupt Request Output that is activatedresulting from a number of conditions. The Interrupt Enableregister allows the user to select events that generate theInterrupt Request Output ...

Page 18 - Physical Connections; 8-Pin PLCC Physical Connections; 8-Pin PLCC Pin Layout

SL811HS Document 38-08008 Rev. *D Page 18 of 32 Physical Connections These parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are theSL811HS and SL811HS-JCT. The 48-pin TQFP packages is the SL811HST-AXC. 28-Pin PLCC Physical Connections 28-Pin PLCC Pi...

Page 19 - GND; Sam ple VDD Generator; Zener; Figure 5. Sample VDD Generator; Part Number

SL811HS Document 38-08008 Rev. *D Page 19 of 32 The diagram below illustrates a simple +3.3V voltage source. Package Markings ( 28-pin PLCC ) YYWW = Date code XXXX = Product code X.X = Silicon revision number +5V (U SB) GND R1 +3.3 V (VDD) Sam ple VDD Generator 45 Ohms 3.9v, 1N52288CT- Zener 2N 2222...

Page 20 - 8-Pin TQFP Physical Connections; 8-Pin TQFP AXC Pin Layout; NC; Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout

SL811HS Document 38-08008 Rev. *D Page 20 of 32 48-Pin TQFP Physical Connections 48-Pin TQFP AXC Pin Layout *See Table 35 on page 21 for Pin and Signal Description for Pins 43 and 44 in Host Mode. 48-Pin TQFP Mechanical Dimensions Note 4. NC. Indicates No Connection. NC Pins must be left unconnected...

Page 21 - 8/28-Pin USB Host Controller Pins Description

SL811HS Document 38-08008 Rev. *D Page 21 of 32 48/28-Pin USB Host Controller Pins Description The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. Thesedevices require a 3.3 VDC power source. The 48-Pin TQFP requires an external 12 or 48 MHz crystal...

Page 24 - Electrical Specifications

SL811HS Document 38-08008 Rev. *D Page 24 of 32 Electrical Specifications Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage tothe device. Exposure to maximum rated conditions for extended periods can affect...

Page 26 - nWR; DATA; I/O Write Cycle to Register or Memory Buffer; Parameter

SL811HS Document 38-08008 Rev. *D Page 26 of 32 Bus Interface Timing Requirements I/O Write Cycle Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns minimum. nWR A0 D0-D7 DATA twr twahld twdhld twasu twdsu twdsu twdhld I/O Wr...

Page 27 - nRD; I/O Read Cycle from Register or Memory Buffer

SL811HS Document 38-08008 Rev. *D Page 27 of 32 I/O Read Cycle Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170 ns minimum. nRD A0 D0-D7 DATA twr twahld twdhld twasu twdsu trdhld I/O Read Cycle from Register or Memory Buffer Re...

Page 28 - DMA Write Cycle; n D R Q; D A T A; n W R

SL811HS Document 38-08008 Rev. *D Page 28 of 32 DMA Write Cycle Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the next nDRQ is not inserted. Parameter Description Min. Typ. Max. tdack nDACK low 80 ns tdwrlo nDACK to nWR low de...

Page 29 - n R D; nRST

SL811HS Document 38-08008 Rev. *D Page 29 of 32 DMA Read Cycle Note Data is held until nDACK goes high regardless of state of nREAD. Reset Timing Note Clock is 48 MHz nominal. Parameter Description Min. Typ. Max. tdack nDACK low 100 ns tddrdlo nDACK to nRD low delay 0 ns tdckdr nDACK low to nDRQ hig...

Page 30 - Clock Timing Specifications; Ordering Information; CLOCK TIMING; trise; Clock HIGH Time; Clock LOW Time; Clock Rise Time; Clock Fall Time; Package Diagrams

SL811HS Document 38-08008 Rev. *D Page 30 of 32 Clock Timing Specifications Ordering Information CLK CLOCK TIMING trise tfall thigh tclk tlow Clock Timing Parameter Description Min. Typ. Max. t CLK Clock Period (48 MHz) 20.0 ns 20.8 ns t HIGH Clock HIGH Time 9 ns 11 ns t LOW Clock LOW Time 9 ns 11 n...

Page 32 - Document History Page; Issue Date

SL811HS Document 38-08008 Rev. *D Page 32 of 32 Document History Page Document Title: SL811HS Embedded USB Host/Slave ControllerDocument Number: 38-08008 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110850 12/14/01 BHA Converted to Cypress format from ScanLogic *A 112687 03/22/02...