Cypress SL811HS - Manual

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Page 2 – Auto Address Increment Mode; Auto Address Increment Example.
Page 3 – PLL Clock Generator; Figure 2; USB Transceiver; on page 4; Figure 2. Full Speed 48 MHz Crystal Circuit; Figure 3. Optional 12 MHz Crystal Circuit
Page 4 – Register Name; SL811HS Host Control Registers
Page 7 – SL811HS Control Registers; Table 10. SL811HS Control Registers Summary
Page 8 – Function
Page 12 – Endpoint Register Set
Page 13 – Endpoint Control Registers; Bit Position
Page 14 – USB Control Registers
Page 16 – Interrupt
Page 18 – Physical Connections; 8-Pin PLCC Physical Connections; 8-Pin PLCC Pin Layout
Page 19 – GND; Sam ple VDD Generator; Zener; Figure 5. Sample VDD Generator; Part Number
Page 20 – 8-Pin TQFP Physical Connections; 8-Pin TQFP AXC Pin Layout; NC; Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout
Page 21 – 8/28-Pin USB Host Controller Pins Description
Page 24 – Electrical Specifications
Page 26 – nWR; DATA; I/O Write Cycle to Register or Memory Buffer; Parameter
Page 27 – nRD; I/O Read Cycle from Register or Memory Buffer
Page 28 – DMA Write Cycle; n D R Q; D A T A; n W R
Page 29 – n R D; nRST
Page 30 – Clock Timing Specifications; Ordering Information; CLOCK TIMING; trise; Clock HIGH Time; Clock LOW Time; Clock Rise Time; Clock Fall Time; Package Diagrams
Page 32 – Document History Page; Issue Date

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SL811HS Embedded USB Host/Slave Controller

SL811HS

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document 38-08008 Rev. *D

Revised February 2, 2007

Features

• First USB Host/Slave controller for embedded systems in

the market with a standard microprocessor bus interface

• Supports both full speed (12 Mbps) and low speed (1.5

Mbps) USB transfer in both master and slave modes

• Conforms to USB Specification 1.1 for full- and low speed

• Operates as a single USB host or slave under software

control

• Automatic detection of either low- or full speed devices

• 8-bit bidirectional data, port I/O (DMA supported in slave

mode)

• On-chip SIE and USB transceivers

• On-chip single root HUB support

• 256-byte internal SRAM buffer

• Ping-pong buffers for improved performance

• Operates from 12 or 48 MHz crystal or oscillator (built-in

DPLL)

• 5V-tolerant interface

• Suspend/resume, wake up, and low-power modes are

supported

• Auto-generation of SOF and CRC5/16

• Auto-address increment mode, saves memory

READ/WRITE cycles

• Development kit including source code drivers is available

• 3.3V power source, 0.35 micron CMOS technology

• Available in both a 28-pin PLCC package and a 48-pin

TQFP package

Introduction

The SL811HS is an Embedded USB Host/Slave Controller
capable of communicating in either full speed or low speed.
The SL811HS interfaces to devices such as microprocessors,
microcontrollers, DSPs, or directly to a variety of buses such
as ISA, PCMCIA, and others. The SL811HS USB Host
Controller conforms to USB Specification 1.1.

The SL811HS incorporates USB Serial Interface functionality
along with internal full or low speed transceivers. The
SL811HS supports and operates in USB full speed mode at 12
Mbps, or in low speed mode at 1.5 Mbps. When in host mode,
the SL811HS is the master and controls the USB bus and the
devices that are connected to it. In peripheral mode, otherwise
known as a slave device, the SL811HS operates as a variety
of full- or low speed devices.

The SL811HS data port and microprocessor interface provide
an 8-bit data path I/O or DMA bidirectional, with interrupt
support to allow easy interface to standard microprocessors or
microcontrollers such as Motorola or Intel CPUs and many
others. The SL811HS has 256-bytes of internal RAM which is
used for control registers and data buffer.

The available package types offered are a 28-pin PLCC
(SL811HS) and the lead-free packages are a 28-pin
(SL811HS-JCT) and a 48-pin (SL811HST-AXC) package. All
packages operate at 3.3 VDC. The I/O interface logic is
5V-tolerant.

X 1

X 2

D -

IN TR

n W R

n R D

n C S

n R S T

D 0-7

G E N E R ATO R

U S B

R o o t H U B

X C V R S

S E R IAL

IN TE R F AC E

E N G IN E

25 6 B yte R AM

B U F F E R S

C O N TR O L

R E G IS TE R S

IN TE R R U P T

C L O C K

C O N TR O L L E R

P R O C E S S O R

IN TE R F AC E

M as ter/S lav e

C o n tro ller

n D R Q

n D AC K

D M A

In terfac e

Block Diagram

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Summary

Page 2 - Auto Address Increment Mode; Auto Address Increment Example.

SL811HS Document 38-08008 Rev. *D Page 2 of 32 Data Port, Microprocessor Interface The SL811HS microprocessor interface provides an 8-bitbidirectional data path along with appropriate control lines tointerface to external processors or controllers. ProgrammedI/O or memory mapped I/O designs are supp...

Page 3 - PLL Clock Generator; Figure 2; USB Transceiver; on page 4; Figure 2. Full Speed 48 MHz Crystal Circuit; Figure 3. Optional 12 MHz Crystal Circuit

SL811HS Document 38-08008 Rev. *D Page 3 of 32 PLL Clock Generator Either a 12 MHz or a 48 MHz external crystal is used with theSL811HS [1] . Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device as shown in Figure 2 and Figure 3 . Use an external clock source if avai...

Page 4 - Register Name; SL811HS Host Control Registers

SL811HS Document 38-08008 Rev. *D Page 4 of 32 “SL811HS Slave Mode Registers” on page 12 describes Slave register definitions). Access to the registers are through themicroprocessor interface similar to normal RAM accesses(see “Bus Interface Timing Requirements” on page 26 ) and provide control and ...