Cypress CYV15G0104TRB - Manuals

Page 2 - Serializer; TX; Deserializer; Reclocker; ROU; Phase; REF

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 2 of 27 The CYV15G0104TRB is ideal for SMPTE applications wheredifferent data rates and serial interface standards arenecessary for each channel. Some applications include multi- format routers, switchers, format converters, SDI monitors,cameras, and c...

Page 3 - Device Configuration and Control Block Diagram

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 3 of 27 INA1+INA1– INA2+INA2– INSELA Clock & Data Recovery PLL Shif ter LFIA 10 RXDA[9:0] Receive Signal Monitor Ou tp ut Regi ste r RXCLKA+RXCLKA– ÷ 2 JTAG Boundary Scan Controller TDO TMS TCLK TDI RESET Reclocking Deserializer Path Block Diagram ...

Page 6 - Table 6

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 6 of 27 Pin DefinitionsCYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDB[9:0] LVTTL Input, synchronous, sampled by TXCLKB ↑ or REFCLKB ↑ [2] Transmit D...

Page 7 - Pin Definitions

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 7 of 27 BISTSTA LVTTL Output, synchronous to the RXCLKA ± output BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0]) displays the status of the BIST reception. See Table 6 for the BIST status reported for each combination of BIST...

Page 12 - Power Control

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 12 of 27 performed by an integrated PLL that tracks the frequency ofthe transitions in the incoming bit stream and aligns the phaseof the internal bit-rate clock to the transitions in the selectedserial data stream. Each CDR accepts a character-rate (b...

Page 13 - Device Configuration and Control Interface; Table 4

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 13 of 27 the device configuration interface. When RXPLLPDA = 0, thereceive PLL and analog circuitry of the channel is disabled.The transmit channel is controlled by the TOE1B and theTOE2B latches via the device configuration interface. Thereclocker fun...

Page 15 - JTAG Support

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 15 of 27 Device Configuration Strategy The following is a series of ordered events needed to load theconfiguration latches on a per channel basis: 1. Pulse RESET Low after device power-up. This operation resets both channels. 2. Set the static latch ba...

Page 16 - Figure 2. Receive BIST State Machine

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 16 of 27 Receive BIST Detected LOW Monitor Data Received {BISTSTA, RXDA[0], No RX PLL Out of Lock Yes, {BISTSTA, RXDA[0], RXDA[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character Auto-Abort Condition Mismatch End-of-BIST State Yes, {BISTSTA, RXDA...

Page 17 - CYV15G0104TRB DC Electrical Characteristics

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 17 of 27 Maximum Ratings (Above which the useful life may be impaired. User guidelinesonly, not tested.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature withPower Applied .........................................

Page 18 - GND; CYV15G0104TRB AC Electrical Characteristics

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 18 of 27 V OLC Output LOW Voltage (V CC Referenced) 100 Ω differential load V CC – 1.4 V CC – 0.7 V 150 Ω differential load V CC – 1.4 V CC – 0.7 V V ODIF Output Differential Voltage|(OUT+) − (OUT − )| 100 Ω differential load 450 900 mV 150 Ω different...

Page 20 - PLL Characteristics

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 20 of 27 t TRGH TRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate) 5.9 ns TRGCLKA HIGH Time (TRGRATEA = 0)(Full Rate) 2.9 [16] ns t TRGL TRGCLKA LOW Time (TRGRATEA = 1)(Half Rate) 5.9 ns TRGCLKA LOW Time (TRGRATEA = 0)(Full Rate) 2.9 [16] ns t TRGD [23] TRGCL...

Page 21 - TXCLKB; Transmit Interface; REFCLKB; REFCLKB selected

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 21 of 27 CYV15G0104TRB Receive PLL Characteristics Over the Operating Range t RXLOCK Receive PLL lock to input data stream (cold start) 376k UI Receive PLL lock to input data stream 376k UI t RXUNLOCK Receive PLL Unlock Rate 46 UI Capacitance [16] Para...

Page 22 - CYV15G0104TRB HOTLink II Transmitter Switching Waveforms; Timing; TXCLKOB; Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver; RXCLKA–

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 22 of 27 CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued) TXCLKOB t TXCLKO Transmit InterfaceTXCLKOB Timing TXRATE = 1 (internal) REFCLKB t REFCLK t REFL t REFH Note 28 Note 29 TXCLKOB t TXCLKO Transmit InterfaceTXCLKOB Timing REFCL...

Page 23 - WREN

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 23 of 27 Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver RXCLKA+ RXDA[9:0] t RXDV+ t RXDV– t RXCLKP Receive InterfaceRead Timing RXCLKA– RXRATEA = 1 ADDR[2:0] t DATAS Bus Configuration Write Timing DATA[6:0] WREN t DATAH t WRENP [+] Feedb...

Page 27 - Document History Page; ISSUE

CYV15G0104TRB Document #: 38-02100 Rev. *B Page 27 of 27 Document History Page Document Title: CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking DeserializerDocument Number: 38-02100 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE ** 244348 See ECN FRE New Data Shee...