Page 4 - CYS25G0101DX-ATC Evaluation Board User’s Guide; Functional Description
CYS25G0101DX-ATC Evaluation Board User’s Guide 4 1. Introduction Cypress's CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communica-tions. It provides complete parallel-to-serial and serial-to-parallel conversions, clock generation, and clock and da...
Page 5 - Figure 1. The Block Diagram of the CYS25G0101DX; RXD; Clock Control
CYS25G0101DX-ATC Evaluation Board User’s Guide 5 Figure 1. The Block Diagram of the CYS25G0101DX TXD15:0 TX PLL x16 /16 RXD 15:0 (155.52MHz) REFCLK (155.52MHz) RXCLKOUT SHIFTER RX CDR PLL TXCLKO Input Register Output Register FIFO (5byte) SHIFTER (155.52MHz) TXCLKI /16 DIAGLOOP LINELOOPLOOPA IN ± OU...
Page 6 - Table 1. Functional Description of the Connectors
CYS25G0101DX-ATC Evaluation Board User’s Guide 6 Figure 2. The CYS25G0101DX Evaluation Board Table 1. Functional Description of the Connectors Jumpers and Connectors Name Description J1 RxD BUS 16-bit RxD Data Bus interface header (see Table 2 for details). Figure 3 shows the orienta- tion of this h...
Page 7 - Figure 3
CYS25G0101DX-ATC Evaluation Board User’s Guide 7 J5 SD This jumper is used to set the SD signal. When open (default), SD signal will be driven by the optical module. When 1-2 are shorted, SD is forced to HIGH. When 2-3 are shorted, SD is forced to LOW. Figure 3 shows the orientation of this jumper J...
Page 10 - Table 4
CYS25G0101DX-ATC Evaluation Board User’s Guide 10 5 LOOPTIME ON The transmission will be using the extracted receive bit-clock for the transmitted bit clock OFF* The transmission will be using the REFCLK input (155.52 MHz), which is multiplied by 16, to generate the transmitted bit clock 6 LOCKREF O...
Page 11 - Figure 3. The Jumper Orientations of the CYS25G0101DX
CYS25G0101DX-ATC Evaluation Board User’s Guide 11 Figure 3. The Jumper Orientations of the CYS25G0101DX J7 J8 LFI GND GND FIFO_ERR RXCLK GND J1 Pin 1 Pin 1 GND GND TXCLKO TXCLKI J2 1 2 3 J5 5B 1B 1A 5A [+] Feedback
Page 12 - to; Diagnostic Loopback Mode; Apply the Testing Hookup illustrated in; Figure 4. Diagnostic Loopback Mode Data Path; TX PLL; REFCLK RXCLKOUT
CYS25G0101DX-ATC Evaluation Board User’s Guide 12 5. Diagnostic Modes The CYS25G0101DX Evaluation Board provides four different diagnostic modes—Diagnostic Loopback mode, Line Loopbackmode, Analog Loopback mode and “Parallel Line Loopback” mode. Figure 4 to Figure 7 illustrate these diagnostic modes...
Page 13 - Figure 5; Figure 5. Line Loopback Mode Data Path; RX CDR
CYS25G0101DX-ATC Evaluation Board User’s Guide 13 5.2 Line Loopback In the Line Loopback mode, serial data (from IN±) will loop through the serial input buffer and CDR block to the serial output buffer(OUT±). Figure 5 shows the data path (bold line) of the Line Loopback mode. To select the Line Loop...
Page 14 - Analog Line Loopback; Figure 6; Figure 6. Analog Line Loopback Mode Data Path; IN
CYS25G0101DX-ATC Evaluation Board User’s Guide 14 5.3 Analog Line Loopback In the Analog Line Loopback mode, serial data (from IN±) will loop through directly from serial input buffer to the serial output buffer(OUT±). Figure 6 shows the data path (bold line) of the Analog Line Loopback mode. To sel...
Page 15 - Figure 7; Test the Internal RX CDR PLL and TX PLL
CYS25G0101DX-ATC Evaluation Board User’s Guide 15 5.4 “Parallel Line Loopback” (TEST0) Mode In Parallel Line Loopback mode, the parallel output buffers are internally linked to the parallel input buffers. Figure 7 shows the data path (bold line) of the Parallel Line Loopback mode. In this test mode,...
Page 16 - Figure 8
CYS25G0101DX-ATC Evaluation Board User’s Guide 16 6. Testing Hookup 6.1 Set-up for BERT Test Figure 8 illustrates the set-up for the BERT test. The equipment list: 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2. Pattern Generator – Tektronix D3186 Pattern Generator 3. Error Detector– ...
Page 17 - Figure 9; Figure 9. Equipment Set-up For Eye Diagram Test
CYS25G0101DX-ATC Evaluation Board User’s Guide 17 6.2 Set-up for Eye Diagram Test Figure 9 illustrates the set-up for testing the Eye Diagram. The equipment list : 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2. Pattern Generator – Tektronix D3186 Pattern Generator 3. Oscilloscope – A...
Page 18 - SONET Jitter Transfer and Jitter Tolerance Test; illustrates the set-up for testing the jitter. The equipment list:; Figure 10. Equipment Set-up For Jitter Test
CYS25G0101DX-ATC Evaluation Board User’s Guide 18 6.3 SONET Jitter Transfer and Jitter Tolerance Test Figure 10 illustrates the set-up for testing the jitter. The equipment list: 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2. SONET Tester – Agilent (HP) OmniBER 718 Communication Perf...
Page 19 - Set-up for Testing the TX PLL in Parallel Line Loopback Mode; External
CYS25G0101DX-ATC Evaluation Board User’s Guide 19 6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode Figure 11 illustrates the set-up for testing the TX PLL in Parallel Line Loopback Mode. The equipment list : 1. Evaluation Board – Cypress CYS25G0101DX Evaluation Board 2. Pattern Gener...
Page 20 - Eye Diagram Testing Result
CYS25G0101DX-ATC Evaluation Board User’s Guide 20 7. Eye Diagram Testing Result Figure 12 is the Eye Diagram measurement from CYS25G0101DX Evaluation Board by using the test set-up as in Figure 9 . In this measurement, the evaluation board is configured to parallel loop back mode ( Figure 7 ) and wi...
Page 21 - Jitter Transfer Testing Result; and
CYS25G0101DX-ATC Evaluation Board User’s Guide 21 8. Jitter Transfer Testing Result Figure 13 and Figure 14 show the Jitter Transfer measurement by using the test set-up as in Figure 10 . Figure 13 is the measurement result of the GR-253 (Bellcore) standard and Figure 14 is the measurement result of...
Page 22 - Jitter Tolerance Testing Result
CYS25G0101DX-ATC Evaluation Board User’s Guide 22 9. Jitter Tolerance Testing Result Figure 15 and Figure 16 show the Jitter Tolerance measurement by using the test set-up as in Figure 10 . Figure 15 is the measurement result of the GR-253 (Bellcore) standard and Figure 16 is the measurement result ...
Page 23 - Appendix A; Description
CYS25G0101DX-ATC Evaluation Board User’s Guide 23 10. Schematic Diagram, PCB Layout and BOM (Bill of Material) Figure 17 to Figure 23 in Appendix A shows the schematic diagram of the CYS25G0101DX evaluation board. Figure 17 is the top level diagram for the schematic diagrams for Figure 18 to Figure ...
Page 24 - Appendix A: Schematic Diagrams of the
CYS25G0101DX-ATC Evaluation Board User’s Guide 24 Appendix A: Schematic Diagrams of the CYS25G0101DX Evaluation Board [+] Feedback
Page 26 - Figure 18. Parallel Output Block Schematic Diagram
CYS25G0101DX-ATC Evaluation Board User’s Guide 26 Figure 18. Parallel Output Block Schematic Diagram [+] Feedback
Page 27 - Figure 19. Parallel Input Block Schematic Diagram
CYS25G0101DX-ATC Evaluation Board User’s Guide 27 Figure 19. Parallel Input Block Schematic Diagram [+] Feedback
Page 28 - Figure 20. Signals Block Schematic Diagram
CYS25G0101DX-ATC Evaluation Board User’s Guide 28 Figure 20. Signals Block Schematic Diagram [+] Feedback
Page 29 - Figure 21. Power Supply Block Schematic Diagram
CYS25G0101DX-ATC Evaluation Board User’s Guide 29 Figure 21. Power Supply Block Schematic Diagram [+] Feedback
Page 30 - Figure 22. Control Block Schematic Diagram
CYS25G0101DX-ATC Evaluation Board User’s Guide 30 Figure 22. Control Block Schematic Diagram [+] Feedback
Page 31 - Figure 23. Reference Clock Block Schematic Diagram
CYS25G0101DX-ATC Evaluation Board User’s Guide 31 Figure 23. Reference Clock Block Schematic Diagram [+] Feedback
Page 32 - Appendix B: PCB Layout Diagrams of the
CYS25G0101DX-ATC Evaluation Board User’s Guide 32 Appendix B: PCB Layout Diagrams of the CYS25G0101DX Evaluation Board [+] Feedback
Page 33 - Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing
CYS25G0101DX-ATC Evaluation Board User’s Guide 33 Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing [+] Feedback
Page 35 - Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout
CYS25G0101DX-ATC Evaluation Board User’s Guide 35 Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout [+] Feedback
Page 37 - Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout
CYS25G0101DX-ATC Evaluation Board User’s Guide 37 Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout [+] Feedback
Page 38 - Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout
CYS25G0101DX-ATC Evaluation Board User’s Guide 38 Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout [+] Feedback
Page 39 - Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen
CYS25G0101DX-ATC Evaluation Board User’s Guide 39 Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen [+] Feedback
Page 40 - Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout
CYS25G0101DX-ATC Evaluation Board User’s Guide 40 Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout [+] Feedback
Page 41 - Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask
CYS25G0101DX-ATC Evaluation Board User’s Guide 41 Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask [+] Feedback
Page 43 - Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4
CYS25G0101DX-ATC Evaluation Board User’s Guide 43 Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4 [+] Feedback
Page 44 - Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4
CYS25G0101DX-ATC Evaluation Board User’s Guide 44 Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4 [+] Feedback
Page 45 - Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4
CYS25G0101DX-ATC Evaluation Board User’s Guide 45 Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4 [+] Feedback
Page 46 - Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4
CYS25G0101DX-ATC Evaluation Board User’s Guide 46 Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4 [+] Feedback