Cypress CYS25G0101DX-ATC - Manual

Cypress CYS25G0101DX-ATC

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Table of Contents:

  • Page 4 – CYS25G0101DX-ATC Evaluation Board User’s Guide; Functional Description
  • Page 5 – Figure 1. The Block Diagram of the CYS25G0101DX; RXD; Clock Control
  • Page 6 – Table 1. Functional Description of the Connectors
  • Page 7 – Figure 3
  • Page 10 – Table 4
  • Page 11 – Figure 3. The Jumper Orientations of the CYS25G0101DX
  • Page 12 – to; Diagnostic Loopback Mode; Apply the Testing Hookup illustrated in; Figure 4. Diagnostic Loopback Mode Data Path; TX PLL; REFCLK RXCLKOUT
  • Page 13 – Figure 5; Figure 5. Line Loopback Mode Data Path; RX CDR
  • Page 14 – Analog Line Loopback; Figure 6; Figure 6. Analog Line Loopback Mode Data Path; IN
  • Page 15 – Figure 7; Test the Internal RX CDR PLL and TX PLL
  • Page 16 – Figure 8
  • Page 17 – Figure 9; Figure 9. Equipment Set-up For Eye Diagram Test
  • Page 18 – SONET Jitter Transfer and Jitter Tolerance Test; illustrates the set-up for testing the jitter. The equipment list:; Figure 10. Equipment Set-up For Jitter Test
  • Page 19 – Set-up for Testing the TX PLL in Parallel Line Loopback Mode; External
  • Page 20 – Eye Diagram Testing Result
  • Page 21 – Jitter Transfer Testing Result; and
  • Page 22 – Jitter Tolerance Testing Result
  • Page 23 – Appendix A; Description
  • Page 24 – Appendix A: Schematic Diagrams of the
  • Page 26 – Figure 18. Parallel Output Block Schematic Diagram
  • Page 27 – Figure 19. Parallel Input Block Schematic Diagram
  • Page 28 – Figure 20. Signals Block Schematic Diagram
  • Page 29 – Figure 21. Power Supply Block Schematic Diagram
  • Page 30 – Figure 22. Control Block Schematic Diagram
  • Page 31 – Figure 23. Reference Clock Block Schematic Diagram
  • Page 32 – Appendix B: PCB Layout Diagrams of the
  • Page 33 – Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing
  • Page 35 – Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout
  • Page 37 – Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout
  • Page 38 – Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout
  • Page 39 – Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen
  • Page 40 – Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout
  • Page 41 – Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask
  • Page 43 – Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4
  • Page 44 – Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4
  • Page 45 – Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4
  • Page 46 – Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4
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Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 19, 2002

CYS25G0101DX-ATC Evaluation Board

User’s Guide

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Summary

Page 4 - CYS25G0101DX-ATC Evaluation Board User’s Guide; Functional Description

CYS25G0101DX-ATC Evaluation Board User’s Guide 4 1. Introduction Cypress's CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communica-tions. It provides complete parallel-to-serial and serial-to-parallel conversions, clock generation, and clock and da...

Page 5 - Figure 1. The Block Diagram of the CYS25G0101DX; RXD; Clock Control

CYS25G0101DX-ATC Evaluation Board User’s Guide 5 Figure 1. The Block Diagram of the CYS25G0101DX TXD15:0 TX PLL x16 /16 RXD 15:0 (155.52MHz) REFCLK (155.52MHz) RXCLKOUT SHIFTER RX CDR PLL TXCLKO Input Register Output Register FIFO (5byte) SHIFTER (155.52MHz) TXCLKI /16 DIAGLOOP LINELOOPLOOPA IN ± OU...

Page 6 - Table 1. Functional Description of the Connectors

CYS25G0101DX-ATC Evaluation Board User’s Guide 6 Figure 2. The CYS25G0101DX Evaluation Board Table 1. Functional Description of the Connectors Jumpers and Connectors Name Description J1 RxD BUS 16-bit RxD Data Bus interface header (see Table 2 for details). Figure 3 shows the orienta- tion of this h...

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