Cypress CY7C1513JV18 - Manuals

Cypress CY7C1513JV18 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1513JV18

Summary

Page 2 - DOFF

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 2 of 27 Logic Block Diagram (CY7C1511JV18) Logic Block Diagram (CY7C1526JV18) 2M x 8 A rr a y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Lo...

Page 3 - Array

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 3 of 27 Logic Block Diagram (CY7C1513JV18) Logic Block Diagram (CY7C1515JV18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D e cod e Read Data Reg. RPS WPS Control Logic Address R...

Page 4 - Pin Configuration

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 4 of 27 Pin Configuration The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1511JV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WP...

Page 6 - Pin Definitions; Application Example

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 6 of 27 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals . Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1511JV18 − D [7:0...

Page 8 - Functional Overview; Read Operations; Write Operations; Single Clock Mode

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 8 of 27 Functional Overview The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18,CY7C1515JV18 are synchronous pipelined Burst SRAMs with aread port and a write port. The read port is dedicated to readoperations and...

Page 9 - to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 9 of 27 Concurrent Transactions The read and write ports on the CY7C1513JV18 operatescompletely independently of one another. As each port latchesthe address inputs on different clock edges, the user can re...

Page 10 - Figure 1; Truth Table; ohms; BUS

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 10 of 27 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example Truth Table The truth table for CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 follo...

Page 12 - BWS

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 12 of 27 Write Cycle Descriptions The write cycle description table for CY7C1515JV18 follows. [2, 10] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L–H – During the Data portion of a write sequence, all four...

Page 13 - Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 13 of 27 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test AccessPort (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TA...

Page 14 - and t; ). The SRAM clock input might not be captured

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 14 of 27 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of the...

Page 15 - TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 15 of 27 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] TEST-LOGIC RESET TEST-LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR 1 0 1 1...

Page 17 - Figure 2

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 17 of 27 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t T...

Page 19 - Boundary Scan Order; Bump ID; Internal

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 19 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7...

Page 20 - Power Up Sequence in QDR-II SRAM; Power Up Sequence; Power Up Waveforms

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 20 of 27 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. DuringPower Up, when the DOFF is tied HIGH, the DLL gets lock...

Page 21 - Maximum Ratings; Operating Range; DC Electrical Characteristics

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 21 of 27 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambien...

Page 22 - Capacitance; Thermal Resistance

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 22 of 27 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, ...

Page 24 - Switching Waveforms

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 24 of 27 Switching Waveforms Figure 3. Read/Write/Deselect Sequence [26, 27, 28] K 1 2 3 4 5 6 7 RPS WPS A Q D C C READ READ WRITE WRITE NOP NOP DON’T CARE UNDEFINED CQ CQ K A0 A1 t KH t KHKH tKL t CYC t tH...

Page 25 - Ordering Information; for actual products offered.

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 25 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (...

Page 26 - Package Diagram

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 26 of 27 Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + ...

Page 27 - Document History Page; ISSUE

Document Number: 001-12560 Rev. *C Revised March 10, 2008 Page 27 of 27 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this documentare the trademarks of their respective holders. CY7...