Cypress CY7C1513JV18 - Manual
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Table of Contents:
- Page 2 – DOFF
- Page 3 – Array
- Page 4 – Pin Configuration
- Page 6 – Pin Definitions; Application Example
- Page 8 – Functional Overview; Read Operations; Write Operations; Single Clock Mode
- Page 9 – to allow the SRAM to adjust its output; Echo Clocks; Switching Characteristics; DLL
- Page 10 – Figure 1; Truth Table; ohms; BUS
- Page 12 – BWS
- Page 13 – Disabling the JTAG Feature; Test Access Port—Test Clock; TAP Registers; Instruction Register; Boundary Scan Register; TAP Instruction Set
- Page 14 – and t; ). The SRAM clock input might not be captured
- Page 15 – TAP Controller State Diagram; The state diagram for the TAP controller follows.; RESET
- Page 17 – Figure 2
- Page 19 – Boundary Scan Order; Bump ID; Internal
- Page 20 – Power Up Sequence in QDR-II SRAM; Power Up Sequence; Power Up Waveforms
- Page 21 – Maximum Ratings; Operating Range; DC Electrical Characteristics
- Page 22 – Capacitance; Thermal Resistance
- Page 24 – Switching Waveforms
- Page 25 – Ordering Information; for actual products offered.
- Page 26 – Package Diagram
- Page 27 – Document History Page; ISSUE
72-Mbit QDR™-II SRAM 4-Word
Burst Architecture
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-12560 Rev. *C
Revised March 10, 2008
Features
■
Separate independent read and write data ports
❐
Supports concurrent transactions
■
300 MHz clock for high bandwidth
■
4-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Single multiplexed address input bus latches address inputs
for read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
QDR-II operates with 1.5 cycle read latency when the Delay
Lock Loop (DLL) is enabled
■
Operates like a QDR-I device with 1 cycle read latency in DLL
off mode
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core V
DD
= 1.8 (± 0.1V); IO V
DDQ
= 1.4V to V
DD
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1511JV18 – 8M x 8
CY7C1526JV18 – 8M x 9
CY7C1513JV18 – 4M x 18
CY7C1515JV18 – 2M x 36
Functional Description
The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and
CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus that exists with common
IO devices. Each port can be accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR-II read and write ports are completely independent
of one another. To maximize data throughput, both read and write
ports are equipped with DDR interfaces. Each address location
is associated with four 8-bit words (CY7C1511JV18), 9-bit words
(CY7C1526JV18), 18-bit words (CY7C1513JV18), or 36-bit
words (CY7C1515JV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
Unit
Maximum Operating Frequency
300
MHz
Maximum Operating Current
x8
1090
mA
x9
1090
x18
1115
x36
1140
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Summary
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 2 of 27 Logic Block Diagram (CY7C1511JV18) Logic Block Diagram (CY7C1526JV18) 2M x 8 A rr a y CLK A (20:0) Gen. K K Control Logic Address Register D [7:0] Read Add . Decode Read Data Reg. RPS WPS Control Lo...
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 3 of 27 Logic Block Diagram (CY7C1513JV18) Logic Block Diagram (CY7C1515JV18) CLK A (19:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D e cod e Read Data Reg. RPS WPS Control Logic Address R...
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Document Number: 001-12560 Rev. *C Page 4 of 27 Pin Configuration The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1511JV18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ A A WP...
