Cypress CY7C1480V25 - Manuals

Cypress CY7C1480V25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1480V25

Summary

Page 4 - Pin Configurations

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 4 of 32 Pin Configurations 100-Pin TQFP Pinout DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C...

Page 5 - TMS

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 5 of 32 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1480V25 (2M x 36) CY7C1482V25 (4M x 18) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE ...

Page 7 - Pin Definitions

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 7 of 32 Pin Definitions Pin Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , an...

Page 8 - Functional Overview; “Truth Table for

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 8 of 32 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access de...

Page 9 - Interleaved Burst Address Table; Linear Burst Address Table

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 9 of 32 DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi- tions are satisfied: (1)...

Page 10 - Truth Table

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 10 of 32 Notes 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.5. The DQ pins are contro...

Page 12 - Disabling the JTAG Feature; TAP Controller; Performing a TAP Reset; TAP Registers; TAP Controller State Diagram; TAP Controller Block Diagram

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 12 of 32 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480V25/CY7C1482V25/CY7C1486V25 incorpo- rates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have...

Page 13 - TAP Instruction Set

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 13 of 32 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the “TAP Controller Block Diagram” on pag...

Page 14 - TAP Timing

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 14 of 32 The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and...

Page 15 - T D O

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 15 of 32 2.5V TAP AC Test Conditions Input pulse levels ................................................ V SS to 2.5V Input rise and fall time ..................................................... 1 nsInput timing reference levels ....

Page 16 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 16 of 32 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order – 165FBGA 73 54 - Boundary Scan Order – 209BGA - - 112 Identification Codes Instr...

Page 19 - Electrical Characteristics

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 19 of 32 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature with...

Page 20 - AC Test Loads and Waveforms

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 20 of 32 Capacitance [14] Parameter Description Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit C ADDRESS Address Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 2.5V V DDQ = 2.5V 6 6 6 pF C DATA Data Input...

Page 21 - Switching Characteristics

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 21 of 32 Notes 15. Timing reference level is 1.25V when V DDQ = 2.5V and is 0.9V when V DDQ = 1.8V. 16. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted. 17. This part has a voltage reg...

Page 22 - Switching Waveforms; Read Cycle Timing

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 22 of 32 Switching Waveforms Read Cycle Timing [21] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW, BWE, BWx Data Out (Q) High-Z t CLZ tDOH tCO ADV t OEHZ t CO Single READ BURST READ tOEV t OELZ t CH...

Page 23 - Write Cycle Timing

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 23 of 32 Write Cycle Timing [21, 22] Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW X D ata Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) ...

Page 24 - Read/Write Cycle Timing

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 24 of 32 Read/Write Cycle Timing [21, 23, 24] Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6) Data In (D) BURST ...

Page 25 - ZZ Mode Timing; CLK

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 25 of 32 ZZ Mode Timing [25, 26] Switching Waveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 25. Device must be deselected when e...

Page 26 - Ordering Information; Commercial

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 26 of 32 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package...

Page 28 - Package Diagrams

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 28 of 32 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NO...

Page 31 - Document History Page; Change

CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 31 of 32 Document History Page Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 38-05282 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 1146...