Cypress CY7C1480V25 - Manual
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Table of Contents:
- Page 4 – Pin Configurations
- Page 5 – TMS
- Page 7 – Pin Definitions
- Page 8 – Functional Overview; “Truth Table for
- Page 9 – Interleaved Burst Address Table; Linear Burst Address Table
- Page 10 – Truth Table
- Page 12 – Disabling the JTAG Feature; TAP Controller; Performing a TAP Reset; TAP Registers; TAP Controller State Diagram; TAP Controller Block Diagram
- Page 13 – TAP Instruction Set
- Page 14 – TAP Timing
- Page 15 – T D O
- Page 16 – Scan Register Sizes; Register Name; Identification Codes; Instruction
- Page 19 – Electrical Characteristics
- Page 20 – AC Test Loads and Waveforms
- Page 21 – Switching Characteristics
- Page 22 – Switching Waveforms; Read Cycle Timing
- Page 23 – Write Cycle Timing
- Page 24 – Read/Write Cycle Timing
- Page 25 – ZZ Mode Timing; CLK
- Page 26 – Ordering Information; Commercial
- Page 28 – Package Diagrams
- Page 31 – Document History Page; Change
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
CY7C1480V25
CY7C1482V25
CY7C1486V25
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05282 Rev. *H
Revised April 23, 2007
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
• 2.5V/1.8V IO operation
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• Single cycle chip deselect
• CY7C1480V25, CY7C1482V25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486V25
available in Pb-free and non-Pb-free 209-ball FBGA
package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
X
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) is active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see
for further details). Write cycles can be one
to two or four bytes wide, as controlled by the byte write control
inputs. When it is active LOW, GW causes all bytes to be
written.
The CY7C1480V25/CY7C1482V25/CY7C1486V25 operates
from a +2.5V core power supply while all outputs may operate
with either a +2.5 or +1.8V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
Note
1. For best practices recommendations, refer to the Cypress application note
System Design Guidelines
at
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
3.0
3.0
3.4
ns
Maximum Operating Current
450
450
400
mA
Maximum CMOS Standby Current
120
120
120
mA
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Summary
CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 4 of 32 Pin Configurations 100-Pin TQFP Pinout DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C...
CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 5 of 32 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1480V25 (2M x 36) CY7C1482V25 (4M x 18) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/288MNC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE ...
CY7C1480V25CY7C1482V25CY7C1486V25 Document #: 38-05282 Rev. *H Page 7 of 32 Pin Definitions Pin Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , an...
