Cypress CY7C1475V25 - Manuals

Cypress CY7C1475V25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1475V25

Summary

Page 4 - Pin Configurations

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 4 of 32 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC/ 288M NC /144M V SS V DD A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DD...

Page 6 - TMS

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 6 of 32 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V25 (2M x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ D DQ D MO...

Page 8 - Pin Definitions

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 8 of 32 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW A , BW...

Page 9 - Functional Overview; “Truth Table for

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 9 of 32 Functional Overview The CY7C1471V25, CY7C1473V25, and CY7C1475V25 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through inp...

Page 10 - Interleaved Burst Address Table; Linear Burst Address Table

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 10 of 32 Because the CY7C1471V25, CY7C1473V25, and CY7C1475V25 are common IO devices, data must not be driven into the device while the outputs are active. The OE can be deasserted HIGH before presenting data to the DQs and DQP X in...

Page 11 - Truth Table

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 11 of 32 Truth Table The truth table for CY7C1471V25, CY7C1473V25, and CY7C1475V25 follows. [2, 3, 4, 5, 6, 7, 8] Operation Address Used CE 1 CE 2 CE 3 ZZ ADV/LD WE BW X OE CEN CLK DQ Deselect Cycle None H X X L L X X X L L->H Tr...

Page 13 - Disabling the JTAG Feature; TAP; Performing a TAP Reset; TAP Controller State Diagram; TAP Controller Block Diagram

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 13 of 32 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471V25, CY7C1473V25, and CY7C1475V25 and incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does n...

Page 14 - TAP Registers; TAP Instruction Set

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 14 of 32 TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data i...

Page 15 - BYPASS; TAP Timing; T e st Clo ck

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 15 of 32 signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.To guarantee that the boundary scan register c...

Page 16 - TAP AC Switching Characteristics

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 16 of 32 TAP AC Switching Characteristics Over the Operating Range [10, 11] Parameter Description Min Max Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH Time 20 ns t TL TCK Clock LOW...

Page 17 - T D O

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 17 of 32 1.8V TAP AC Test Conditions Input pulse levels ..................................... 0.2V to V DDQ – 0.2 Input rise and fall time ..................................................... 1 nsInput timing reference levels ........

Page 18 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 18 of 32 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order – 165FBGA 71 52 - Boundary Scan Order – 209BGA - - 110 Identification Codes Instr...

Page 21 - Electrical Characteristics

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 21 of 32 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature with Pow...

Page 23 - Switching Characteristics

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 23 of 32 Switching Characteristics Over the Operating Range. Timing reference level is 1.25V when V DDQ = 2.5V and is 0.9V when V DDQ = 1.8V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 22 unless otherwise ...

Page 24 - Switching Waveforms; Figure 1

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 24 of 32 Switching Waveforms Figure 1 shows read-write timing waveform. [19, 20, 21] Figure 1. Read/Write Timing W R ITE D(A 1) 1 2 3 4 5 6 7 8 9 CLK tCY C tCL tCH 10 CE tCEH tCES W E CE N tCENH tCENS B W X A DV /LD tA H tA S A DDR ...

Page 26 - Mode Timing; CLK

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 26 of 32 Figure 3 shows ZZ Mode timing waveform. [23, 24] Figure 3. ZZ Mode Timing Switching Waveforms (continued) t ZZ I SU PPLY CLK ZZ t ZZR E C A LL IN PU T S (e xce pt ZZ) D O N ’ T CA R E I D D ZZ t ZZI t R ZZI O u t pu t s (Q ...

Page 27 - Ordering Information; for actual products offered.

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 27 of 32 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package...

Page 28 - Package Diagrams

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 28 of 32 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NO...

Page 31 - Document History Page; with NoBLTM Architecture

CY7C1471V25CY7C1473V25CY7C1475V25 Document #: 38-05287 Rev. *I Page 31 of 32 Document History Page Document Title: CY7C1471V25/CY7C1473V25/CY7C1475V25, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05287 REV. ECN NO. Issue Date Orig. of Change Descri...