Cypress CY7C1473BV25 - Manuals

Cypress CY7C1473BV25 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1473BV25

Summary

Page 4 - Pin Configurations

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 4 of 30 Pin Configurations A A A A A1 A0 NC/288M NC/ 144M V SS V DD A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ A DQ...

Page 6 - TMS

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 6 of 30 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV25 (2M x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ...

Page 9 - Functional Overview; Single Read Accesses; “Truth Table for

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 9 of 30 Functional Overview The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25are synchronous flow through burst SRAMs designed specifi-cally to eliminate wait states during write read transitions. Allsynchronous inputs pass th...

Page 10 - ZZ Mode Electrical Characteristics

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 10 of 30 included to greatly simplify read/modify/write sequences, whichcan be reduced to simple byte write operations. Because the CY7C1471BV25, CY7C1473BV25, andCY7C1475BV25 are common IO devices, data must not bedriven int...

Page 13 - Disabling the JTAG Feature; through a pull up resistor. TDO must be left unconnected.; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; Figure 3. TAP Controller State Diagram; Figure 4. TAP Controller Block Diagram

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 13 of 30 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25incorporate a serial boundary scan Test Access Port (TAP). Thisport operates in accordance with IEEE Standard 1149.1-1990but doe...

Page 14 - TAP Registers; “TAP Controller Block Diagram”; BYPASS instruction is executed.; TAP Instruction Set; “Identification

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 14 of 30 TAP Registers Registers are connected between the TDI and TDO balls andenable the scanning of data into and out of the SRAM testcircuitry. Only one register is selectable at a time through theinstruction register. Da...

Page 15 - plus t; BYPASS; Figure 5. TAP Timing; T e st Clo ck

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 15 of 30 no guarantee as to the value that is captured. Repeatable resultsmay not be possible. To guarantee that the boundary scan register captures thecorrect signal value, make certain that the SRAM signal is stabi-lized lo...

Page 16 - T D O; TAP DC Electrical Characteristics And Operating Conditions

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 16 of 30 2.5V TAP AC Test Conditions Input pulse levels ................................................. V SS to 2.5V Input rise and fall time ..................................................... 1 ns Input timing reference...

Page 20 - Electrical Characteristics

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 20 of 30 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature w...

Page 22 - Switching Characteristics; “AC Test Loads and

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 22 of 30 Switching Characteristics Over the Operating Range. Timing reference level is 1.25V when V DDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 21 unless otherwise noted. Parameter Descri...

Page 23 - Switching Waveforms; Figure 8

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 23 of 30 Switching Waveforms Figure 8 shows read-write timing waveform. [19, 20, 21] Figure 8. Read/Write Timing W R ITE D(A 1) 1 2 3 4 5 6 7 8 9 CLK tCY C tCL tCH 10 CE tCEH tCES W E CE N tCENH tCENS B W X A DV /LD tA H tA S...

Page 24 - Figure 9. NOP, STALL and DESELECT Cycles

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 24 of 30 Figure 9 shows NOP, STALL and DESELECT Cycles waveform. [19, 20, 22] Figure 9. NOP, STALL and DESELECT Cycles Switching Waveforms (continued) READ Q(A3) 4 5 6 7 8 9 10 A3 A4 A5 D(A4) 1 2 3 CLK CE WE CEN BW [A:D] ADV/...

Page 25 - shows ZZ Mode timing waveform.; Mode Timing; CLK

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 25 of 30 Figure 10 shows ZZ Mode timing waveform. [23, 24] Figure 10. ZZ Mode Timing Switching Waveforms (continued) t ZZ I SU PPLY CLK ZZ t ZZR E C A LL IN PU T S (e xce pt ZZ) D O N ’ T CA R E I D D ZZ t ZZI t R ZZI O u t p...

Page 26 - Ordering Information; for actual products offered.

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 26 of 30 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code ...

Page 27 - Package Diagrams

CY7C1471BV25 CY7C1473BV25, CY7C1475BV25 Document #: 001-15013 Rev. *E Page 27 of 30 Package Diagrams Figure 11. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH ...

Page 30 - Document History Page; Issue

Document #: 001-15013 Rev. *E Revised February 29, 2008 Page 30 of 30 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in thisdocument may be the trademarks of their respecti...