Cypress CY7C1471BV33 - Manuals

Cypress CY7C1471BV33 – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1471BV33

Summary

Page 4 - Pin Configuration

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 4 of 32 Pin Configuration A A A A A1 A0 NC/288M NC /144M V SS V DD A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ A DQP...

Page 6 - TMS

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 6 of 32 Pin Configuration (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471BV33 (2M x 36) CY7C1473BV33 (4M x 18) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 ...

Page 8 - Pin Definitions

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 8 of 32 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the Address Locations . Sampled at the rising edge of the CLK. A [1:0] is fed to the two-bit burst counter. BW ...

Page 9 - Functional Overview; Single Read Accesses

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 9 of 32 Functional Overview The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33are synchronous flow through burst SRAMs designedspecifically to eliminate wait states during write-read transitions.All synchronous inputs pass thro...

Page 10 - Single Write Accesses; Truth Table for; Burst Write Accesses; Single Write; Sleep Mode; Interleaved Burst Address Table

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 10 of 32 Single Write Accesses Write accesses are initiated when the following conditions aresatisfied at clock rise: (1) CEN is asserted LOW, (2) CE 1 , CE 2 , and CE 3 are all asserted active, and (3) WE is asserted LOW. Th...

Page 11 - Truth Table

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 11 of 32 The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows. [1, 2, 3, 4, 5, 6, 7] Truth Table Operation Address Used CE 1 CE 2 CE 3 ZZ ADV/LD WE BW X OE CEN CLK DQ Deselect Cycle None H X X L L X X X L ...

Page 13 - Disabling the JTAG Feature; Performing a TAP Reset; TAP Registers; nstruction Register; Boundary Scan Register

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 13 of 32 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33incorporate a serial boundary scan test access port (TAP). Thisport operates in accordance with IEEE Standard 1149.1-1990but doe...

Page 14 - TAP Instruction Set; “Identification

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 14 of 32 TAP Instruction Set Overview Eight different instructions are possible with the three-bitinstruction register. All combinations are listed in “Identification Codes” on page 19. Three of these instructions are listed ...

Page 15 - TAP Controller State Diagram; R E SE T

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 15 of 32 TAP Controller State Diagram T E ST -LO G IC R E SE T R U N -T E ST / ID LE SE LE CT D R -SCA N SE LE CT IR -SCA N CA PT U R E -D R SH IFT -D R CA PT U R E -IR SH IFT -IR E X IT 1-D R PA U SE -D R E X IT 1-IR PA U SE...

Page 16 - TAP Controller Block Diagram

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 16 of 32 TAP Controller Block Diagram B ypa ss R egister 0 Instr u ctio n R egister 0 1 2 Identifi ca tio n R egister 0 1 2 29 30 31 . . . B o u nda r y Sca n R egister 0 1 2 . . x . . . Select io n Cir cu it r y T CK T M S T...

Page 17 - V TAP AC Output Load Equivalent; T D O; TAP DC Electrical Characteristics and Operating Conditions

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 17 of 32 3.3V TAP AC Test Conditions Input pulse levels .................................................V SS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference l...

Page 18 - T e st Clo ck

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 18 of 32 TAP Timing Figure 3. TAP Timing TAP AC Switching Characteristics Over the Operating Range [10, 11] Parameter Description Min Max Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK C...

Page 22 - Electrical Characteristics

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 22 of 32 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature w...

Page 24 - Switching Characteristics

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 24 of 32 Switching Characteristics Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when V DDQ = 3.3V and is 1.25V when V DDQ = 2.5V. Test conditions shown in (a) of AC T...

Page 25 - Switching Waveforms; Figure 5

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 25 of 32 Switching Waveforms Figure 5 shows read-write timing waveform. [20, 21, 22] Figure 5. Read/Write Timing W R ITE D(A 1) 1 2 3 4 5 6 7 8 9 CLK tCY C tCL tCH 10 CE tCEH tCES W E CE N tCENH tCENS B W X A DV /LD tA H tA S...

Page 27 - Mode Timing; CLK

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 27 of 32 Figure 7 shows ZZ Mode timing waveform. [24, 25] Figure 7. ZZ Mode Timing Switching Waveforms (continued) t ZZ I SU PPLY CLK ZZ t ZZR E C A LL IN PU T S (e xce pt ZZ) D O N ’ T CA R E I D D ZZ t ZZI t R ZZI O u t pu ...

Page 28 - Ordering Information; for actual products offered.

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 28 of 32 Ordering Information Not all of the speed, package, and temperature ranges mentioned here are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz...

Page 29 - Package Diagrams

CY7C1471BV33 CY7C1473BV33, CY7C1475BV33 Document #: 001-15029 Rev. *B Page 29 of 32 Package Diagrams Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT E...

Page 32 - Document History Page; Issue; See ECN

Document #: 001-15029 Rev. *B Revised March 05, 2008 Page 32 of 32 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this documentare the trademarks of their respective hold...