Cypress CY7C1443AV33 - Manuals

Cypress CY7C1443AV33 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1443AV33

Summary

Page 4 - Pin Configurations

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 4 of 31 Pin Configurations Figure 1. 100-Pin TQFP Pinout A A A A A 1 A 0 NC/ 72M A V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ...

Page 5 - TMS

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 5 of 31 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1441AV33 (1M x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C D...

Page 7 - Pin Definitions

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 7 of 31 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs Used to Select One of the Address Location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , an...

Page 9 - Functional Overview

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 9 of 31 Functional Overview All synchronous inputs pass through input registers controlled bythe rising edge of the clock. Maximum access delay from theclock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1441AV33/CY7C1443AV...

Page 12 - Disabling the JTAG Feature; through a pull up resistor. TDO should be; Performing a TAP Reset; TAP Controller State Diagram

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 12 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incor-porates a serial boundary scan test access port (TAP). This partis fully compliant with 1149.1. The TAP operates usingJEDEC-stand...

Page 13 - BYPASS instruction is executed.; TAP Instruction Set; and t; ). The SRAM clock input might not be captured

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 13 of 31 Instruction Register Three-bit instructions can be serially loaded into the instructionregister. This register is loaded when it is placed between the TDIand TDO balls as shown in the Tap Controller Block Diagram.Upon ...

Page 14 - TAP Timing; Test Clock

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 14 of 31 EXTEST The EXTEST instruction drives the preloaded data out throughthe system output pins. This instruction also connects theboundary scan register for serial access between the TDI andTDO in the shift-DR controller st...

Page 15 - TAP AC Switching Characteristics

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 15 of 31 TAP AC Switching Characteristics Over the Operating Range [9, 10] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clo...

Page 16 - V TAP AC Output Load Equivalent; T DO; TAP DC Electrical Characteristics And Operating Conditions; Parameter

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 16 of 31 3.3V TAP AC Test Conditions Input pulse levels ................................................ .V SS to 3.3V Input rise and fall times....................................................1 ns Input timing reference lev...

Page 18 - 65-ball FBGA Boundary Scan Order; Ball ID; Internal

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 18 of 31 165-ball FBGA Boundary Scan Order [13,14] CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18) Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 26 E11 51 A3 76 N1 2 N7 27 D11 52 A2 77 N2 3 N10 28 G10 53 B2 78 P1 ...

Page 19 - Electrical Characteristics; DC Electrical Characteristics

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 19 of 31 Maximum Ratings Exceeding maximum ratings may shorten the useful life of thedevice. User guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPowe...

Page 21 - Switching Characteristics

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 21 of 31 Switching Characteristics Over the Operating Range [22, 23] Parameter Description –133 –100 Unit Min. Max. Min. Max. t POWER V DD (Typical) to the first Access [18] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Cl...

Page 22 - Timing Diagrams; Figure 3. Read Cycle Timing

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 22 of 31 Timing Diagrams Figure 3. Read Cycle Timing [24] . tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 t CEH tCES Data Out (Q) High-Z t CLZ tDOH tCDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps aroun...

Page 23 - Figure 4. Write Cycle Timing

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 23 of 31 Figure 4. Write Cycle Timing [24, 25] . Timing Diagrams (continued) t CYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A...

Page 25 - Figure 6. ZZ Mode Timing; CLK

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 25 of 31 Figure 6. ZZ Mode Timing [28, 29] Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Note 28. Device must be deselec...

Page 26 - Ordering Information; for actual products offered.

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 26 of 31 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative orvisit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Pac...

Page 27 - Package Diagrams

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 27 of 31 Package Diagrams Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 ...

Page 30 - Document History Page; Issue Date

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 30 of 31 Document History Page Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAMDocument Number: 38-05357 REV. ECN NO. Issue Date Orig. of Change Description of Change ...