Cypress CY7C1443AV33 - Manual
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Table of Contents:
- Page 4 – Pin Configurations
- Page 5 – TMS
- Page 7 – Pin Definitions
- Page 9 – Functional Overview
- Page 12 – Disabling the JTAG Feature; through a pull up resistor. TDO should be; Performing a TAP Reset; TAP Controller State Diagram
- Page 13 – BYPASS instruction is executed.; TAP Instruction Set; and t; ). The SRAM clock input might not be captured
- Page 14 – TAP Timing; Test Clock
- Page 15 – TAP AC Switching Characteristics
- Page 16 – V TAP AC Output Load Equivalent; T DO; TAP DC Electrical Characteristics And Operating Conditions; Parameter
- Page 18 – 65-ball FBGA Boundary Scan Order; Ball ID; Internal
- Page 19 – Electrical Characteristics; DC Electrical Characteristics
- Page 21 – Switching Characteristics
- Page 22 – Timing Diagrams; Figure 3. Read Cycle Timing
- Page 23 – Figure 4. Write Cycle Timing
- Page 25 – Figure 6. ZZ Mode Timing; CLK
- Page 26 – Ordering Information; for actual products offered.
- Page 27 – Package Diagrams
- Page 30 – Document History Page; Issue Date
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05357 Rev. *G
Revised May 09, 2008
Features
■
Supports 133-MHz bus operations
■
1M x 36/2M x 18/512K x 72 common IO
■
3.3V core power supply
■
2.5V or 3.3V IO power supply
■
Fast clock-to-output times
❐
6.5 ns (133-MHz version)
■
Provide high-performance 2-1-1-1 access rate
■
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
CY7C1441AV33, CY7C1443AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non-lead-free 165-ball FBGA package. CY7C1447AV33
available in Pb-free and non-lead-free 209-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” Sleep Mode option
Functional Description
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
[1]
are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW
x
, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
310
290
mA
Maximum CMOS Standby Current
120
120
mA
Note
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
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Summary
CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 4 of 31 Pin Configurations Figure 1. 100-Pin TQFP Pinout A A A A A 1 A 0 NC/ 72M A V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ...
CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 5 of 31 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1441AV33 (1M x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C D...
CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document #: 38-05357 Rev. *G Page 7 of 31 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs Used to Select One of the Address Location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , an...
