Cypress CY7C1380D - Manuals

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Manual

Manual Cypress CY7C1380D

Summary

Page 3 - Pin Configurations

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 3 of 34 Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(512K X 36) Figure 2. CY7C1382D, CY7C1382F (1M X 18) [+] Feedback

Page 8 - Functional Overview; Single Read Accesses

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 8 of 34 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum a...

Page 10 - Truth Table

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 10 of 34 Truth Table The Truth Table for this data sheet follows. [4, 5, 6, 7, 8] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect C...

Page 12 - Disabling the JTAG Feature; TAP Controller State Diagram; TAP Controller Block Diagram; Performing a TAP Reset; TAP Registers; Instruction Register

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 12 of 34 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380D/CY7C1382D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V...

Page 13 - “Identification Register Definitions”; TAP Instruction Set; “Identification

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 13 of 34 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save ti...

Page 14 - Reserved; TAP Timing

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 14 of 34 when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit can be set by enter...

Page 15 - TDO; TAP DC Electrical Characteristics And Operating Conditions

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 15 of 34 3.3V TAP AC Test Conditions Input pulse levels ................................................. V SS to 3.3V Input rise and fall times....................................................1 nsInput timing reference l...

Page 17 - 19-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 17 of 34 119-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 ...

Page 18 - 65-Ball BGA Boundary Scan Order

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 18 of 34 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9...

Page 19 - Electrical Characteristics

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 19 of 34 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. Storage Temperature ................................. –65°C to +150°CAmbient Temperature with ...

Page 21 - Figure 9. AC Test Loads and Waveforms

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 21 of 34 Figure 9. AC Test Loads and Waveforms OUTPUT R = 317 Ω R = 351 Ω 5 pF INCLUDING JIG AND SCOPE (a) (b) OUTPUT R L = 50 Ω Z 0 = 50 Ω V T = 1.5V 3.3V ALL INPUT PULSES V DDQ GND 90% 10% 90% 10% ≤ 1 ns ≤ 1 ns (c) OUTPUT ...

Page 22 - Switching Characteristics

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 22 of 34 Switching Characteristics Over the Operating Range [20, 21] Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max t POWER V DD (Typical) to the first Access [22] 1 1 1 ms Clock t CYC Clock Cycle...

Page 23 - Switching Waveforms; Figure 10. Read Cycle Timing

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 23 of 34 Switching Waveforms Figure 10. Read Cycle Timing [26] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW, BWE, BWx Data Out (Q) High-Z t CLZ tDOH tCO ADV t OEHZ t CO Single READ BURST RE...

Page 24 - Figure 11. Write Cycle Timing

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 24 of 34 Figure 11. Write Cycle Timing [26, 27] Switching Waveforms (continued) t CYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW X ata Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1)...

Page 26 - Figure 13. ZZ Mode Timing

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 26 of 34 Figure 13. ZZ Mode Timing [30, 31] Switching Waveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30. Device must be...

Page 27 - Ordering Information

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 27 of 34 Ordering Information The following table lists all speed, package and temperature range options. Please note that some options listed below may not be available for order entry. To verify the availability of a speci...

Page 30 - Package Diagrams

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 30 of 34 Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLA...

Page 33 - Document History Page; Date

CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 33 of 34 Document History Page Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05543 REV. ECN NO. Submission Date Orig. of Change Description of Change ...