Cypress CY7C1380D - Manual
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Table of Contents:
- Page 3 – Pin Configurations
- Page 8 – Functional Overview; Single Read Accesses
- Page 10 – Truth Table
- Page 12 – Disabling the JTAG Feature; TAP Controller State Diagram; TAP Controller Block Diagram; Performing a TAP Reset; TAP Registers; Instruction Register
- Page 13 – “Identification Register Definitions”; TAP Instruction Set; “Identification
- Page 14 – Reserved; TAP Timing
- Page 15 – TDO; TAP DC Electrical Characteristics And Operating Conditions
- Page 17 – 19-Ball BGA Boundary Scan Order; Ball ID; Internal
- Page 18 – 65-Ball BGA Boundary Scan Order
- Page 19 – Electrical Characteristics
- Page 21 – Figure 9. AC Test Loads and Waveforms
- Page 22 – Switching Characteristics
- Page 23 – Switching Waveforms; Figure 10. Read Cycle Timing
- Page 24 – Figure 11. Write Cycle Timing
- Page 26 – Figure 13. ZZ Mode Timing
- Page 27 – Ordering Information
- Page 30 – Package Diagrams
- Page 33 – Document History Page; Date
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05543 Rev. *F
Revised January 12, 2009
Features
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3V core power supply
■
2.5V or 3.3V I/O power supply
■
Fast clock-to-output times
❐
2.6 ns (for 250 MHz device)
■
Provides high performance 3-1-1-1 access rate
■
User selectable burst counter supporting Intel
Pentium
®
inter-
leaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1380D/CY7C1382D is available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package; CY7C1380F/CY7C1382F is available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 119-ball BGA and 165-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
ZZ sleep mode option
Functional Description
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE
1
),
depth-expansion chip enables (CE
2
and CE
3
), burst control
inputs (ADSC, ADSP, and ADV), write enables (BW
X
, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see
on page 6 and
for further details). Write cycles can be one to two or four bytes
wide as controlled by the byte write control inputs. GW when
active LOW causes all bytes to be written.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
2.6
3.0
3.4
ns
Maximum Operating Current
350
300
275
mA
Maximum CMOS Standby Current
70
70
70
mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064,
SRAM System Design Guidelines
on
www.cypress.com
.
2. CE
3,
CE
2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
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Summary
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 3 of 34 Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(512K X 36) Figure 2. CY7C1382D, CY7C1382F (1M X 18) [+] Feedback
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 8 of 34 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum a...
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev. *F Page 10 of 34 Truth Table The Truth Table for this data sheet follows. [4, 5, 6, 7, 8] Operation Add. Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect C...
