Cypress CY7C138 - Manuals - manualsarea.com

Page 2 - Pin Configurations; Notes

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 2 of 17 Pin Configurations Figure 1. 68-Pin PLCC (Top View) \ Table 1. Pin Definitions Left Port Right Port Description I/O 0L–7L(8L) I/O 0R–7R(8R) Data Bus Input/Output A 0L–11L A 0R–11R Address Lines CE L CE R Chip Enable OE L OE R Output Enable R...

Page 3 - Electrical Characteristics

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 3 of 17 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. [5] Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature with Power Applied .....

Page 5 - Note; Switching Characteristics

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 5 of 17 Figure 2. AC Test Loads and Waveforms 3.0V GND 90% 90% 10% < 3 ns < 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 893 Ω 5V OUTPUT R2 = 347 Ω C = 30 pF R TH = 250 Ω V TH = 1.4V OUTPUT C = 30pF (b) Thé venin Equivalent(Load 1) ...

Page 6 - Switching Waveforms; DATA VALID

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 6 of 17 t HD Data Hold From Write End 0 0 0 0 ns t HZWE [11,12] R/W LOW to High Z 10 15 20 25 ns t LZWE [11,12] R/W HIGH to Low Z 3 3 3 3 ns t WDD [13] Write Pulse to Data Delay 30 50 60 70 ns t DDD [13] Write Data Valid to Read Data Valid 25 30 35 ...

Page 8 - Figure 8. Semaphore Read After Write Timing, Either Side

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 8 of 17 Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port) [22, 24, 25] Figure 8. Semaphore Read After Write Timing, Either Side [26] Switching Waveforms (continued) t AW t WC DATA VALID HIGH IMPEDANCE t SCE t SA t PWE t HD t SD t...

Page 9 - Figure 9. Timing Diagram of Semaphore Contention

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 9 of 17 Figure 9. Timing Diagram of Semaphore Contention [27, 28, 29] Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH) [21] Switching Waveforms (continued) t SOP t AA SEM R/W OE I/O 0 VALID ADDRESS VALID ADDRESS t HD DATA IN VALID DATA OUT V...

Page 11 - CE

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 11 of 17 Figure 13. Busy Timing Diagram No. 2 (Address Arbitration) [30] Note 30. If t PS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. Switching Waveforms (con...

Page 12 - Figure 14. Interrupt Timing Diagrams; Left Side Sets INT

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 12 of 17 Figure 14. Interrupt Timing Diagrams Notes 31. t HA depends on which enable pin (CE L or R/W L ) is deasserted first. 32. t INS or t INR depends on which enable pin (CE L or R/W L ) is asserted last. Switching Waveforms (continued) WRITE FF...

Page 13 - Write Operation; Table 3; Read Operation; Table 4; Busy; Table 5

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 13 of 17 Architecture The CY7C138/9 consists of an array of 4K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location ...

Page 15 - Figure 15. Typical DC and AC Characteristics

CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 15 of 17 Figure 15. Typical DC and AC Characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 –55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 OUT P UT SOURC E CURRENT (mA) SUPPLY VOLTAGE (V) NORMALIZED SUPPLY CURRENTvs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT ...

Page 17 - Worldwide Sales and Design Support; Change

Document #: 38-06037 Rev. *D Revised March 12, 2009 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C138, CY7C139 © Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change withou...