Cypress CY7C138 - Manual
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Table of Contents:
- Page 2 – Pin Configurations; Notes
- Page 3 – Electrical Characteristics
- Page 5 – Note; Switching Characteristics
- Page 6 – Switching Waveforms; DATA VALID
- Page 8 – Figure 8. Semaphore Read After Write Timing, Either Side
- Page 9 – Figure 9. Timing Diagram of Semaphore Contention
- Page 11 – CE
- Page 12 – Figure 14. Interrupt Timing Diagrams; Left Side Sets INT
- Page 13 – Write Operation; Table 3; Read Operation; Table 4; Busy; Table 5
- Page 15 – Figure 15. Typical DC and AC Characteristics
- Page 17 – Worldwide Sales and Design Support; Change
CY7C138, CY7C139
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-06037 Rev. *D
Revised March 12, 2009
Features
■
True Dual-Ported memory cells that enable simultaneous reads
of the same memory location
■
4K x 8 organization (CY7C138)
■
4K x 9 organization (CY7C139)
■
0.65-micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: I
CC
= 160 mA (max.)
■
Fully asynchronous operation
■
Automatic power down
■
TTL compatible
■
Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Available in 68-pin PLCC
■
Pb-free packages available
Functional Description
The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9 can
be used as a standalone 8/9-bit dual-port static RAM or multiple
devices can be combined to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multipro-
cessor designs, communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Logic Block Diagram
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Summary
CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 2 of 17 Pin Configurations Figure 1. 68-Pin PLCC (Top View) \ Table 1. Pin Definitions Left Port Right Port Description I/O 0L–7L(8L) I/O 0R–7R(8R) Data Bus Input/Output A 0L–11L A 0R–11R Address Lines CE L CE R Chip Enable OE L OE R Output Enable R...
CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 3 of 17 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. [5] Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature with Power Applied .....
CY7C138, CY7C139 Document #: 38-06037 Rev. *D Page 5 of 17 Figure 2. AC Test Loads and Waveforms 3.0V GND 90% 90% 10% < 3 ns < 3 ns 10% ALL INPUT PULSES (a) Normal Load (Load 1) R1 = 893 Ω 5V OUTPUT R2 = 347 Ω C = 30 pF R TH = 250 Ω V TH = 1.4V OUTPUT C = 30pF (b) Thé venin Equivalent(Load 1) ...
