Cypress CY7C1373D - Manuals

Cypress CY7C1373D – Manual in PDF format online.

Manuals:

Manual

Manual Cypress CY7C1373D

Summary

Page 3 - Pin Configurations

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 3 of 29 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC/ 288M NC /144M V SS V DD NC /36M A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A ...

Page 6 - TMS

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 6 of 29 Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1371D (512K x 36) 2 3 4 5 6 7 1 ABCD E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC/...

Page 7 - Pin Definitions

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 7 of 29 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW A , BW B BW C , BW D ...

Page 8 - Functional Overview

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 8 of 29 Functional Overview The CY7C1371D/CY7C1373D is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising...

Page 9 - Interleaved Burst Address Table; ZZ Mode Electrical Characteristics

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 9 of 29 details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle.The data written during the Write operation is controlled by BW X signals. The CY7C1371D/CY7C137...

Page 11 - Disabling the JTAG Feature; Performing a TAP Reset; TAP Registers; Instruction Register; TAP Controller State Diagram; TAP Controller Block Diagram

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 11 of 29 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels.The CY...

Page 12 - TAP Instruction Set

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 12 of 29 instruction if the controller is placed in a reset state as described in the previous section.When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isol...

Page 13 - TAP Timing; Test Clock

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 13 of 29 boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register ...

Page 14 - TAP AC Switching Characteristics

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 14 of 29 TAP AC Switching Characteristics Over the Operating Range [10, 11] Parameter Description Min Max Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clock LOW time 20 ns Out...

Page 15 - V TAP AC Output Load Equivalent; T D O; TAP DC Electrical Characteristics And Operating Conditions

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 15 of 29 3.3V TAP AC Test Conditions Input pulse levels ............................................... .V SS to 3.3V Input rise and fall times ................................................... 1 nsInput timing reference levels ....................

Page 17 - 19-Ball BGA Boundary Scan Order; Ball ID; Internal

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 17 of 29 119-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 ...

Page 18 - 65-Ball BGA Boundary Scan Order

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 18 of 29 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C...

Page 19 - Electrical Characteristics

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 19 of 29 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Applied ............

Page 21 - Switching Characteristics

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 21 of 29 Switching Characteristics Over the Operating Range [23, 24] Parameter Description 133 MHz 100 MHz Unit Min Max Min Max t POWER [19] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 2.1 2.5 ns t CL Clock LOW 2.1 2.5 ns Output ...

Page 22 - Switching Waveforms

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 22 of 29 Switching Waveforms Read/Write Waveforms [25, 26, 27] W R ITE D(A 1) 1 2 3 4 5 6 7 8 9 CLK tCY C tCL tCH 10 CE tCEH tCES W E CE N tCENH tCENS B W X A DV /LD tA H tA S A DDR E SS A 1 A 2 A 3 A 4 A 5 A 6 A 7 tDH tDS DQ CO M M A N D tCLZ D(A...

Page 23 - NOP, STALL AND DESELECT Cycles

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 23 of 29 NOP, STALL AND DESELECT Cycles [25, 26, 28] Switching Waveforms (continued) READ Q(A3) 4 5 6 7 8 9 10 A3 A4 A5 D(A4) 1 2 3 CLK CE WE CEN BW [A:D] ADV/LD ADDRESS DQ COMMAND WRITE D(A4) STALL WRITE D(A1) READ Q(A2) STALL NOP READ Q(A5) DESE...

Page 24 - ZZ Mode Timing; CLK

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 24 of 29 ZZ Mode Timing [29, 30] Switching Waveforms (continued) t ZZ I SU PPLY CLK ZZ t ZZR E C A LL IN PU T S (e xce pt ZZ) D O N ’ T CA R E I D D ZZ t ZZI t R ZZI O u t pu t s (Q ) H igh -Z D E SE LE CT o r R E A D O n ly Notes: 29. Device must...

Page 25 - Ordering Information

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 25 of 29 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part a...

Page 26 - Package Diagrams

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 26 of 29 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098...

Page 29 - Document History Page; Issue

CY7C1371DCY7C1373D Document #: 38-05556 Rev. *F Page 29 of 29 Document History Page Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Architecture Document Number: 38-05556 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 254513 See ECN ...