Cypress CY7C1364C - Manuals

Cypress CY7C1364C – Manual in PDF format online.

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Manual

Manual Cypress CY7C1364C

Summary

Page 2 - Selection Guide; Unit; Pin Configuration

CY7C1364C Document #: 38-05689 Rev. *E Page 2 of 18 Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA Pin Configuration A A A A A 1 A 0 NC NC V SS V DD NC NC A A A A A A A NCDQ B DQ B V DD...

Page 4 - Pin Definitions

CY7C1364C Document #: 38-05689 Rev. *E Page 4 of 18 Pin Definitions Name TQFP I/O Description A 0 , A 1 , A 37, 36, 32, 33, 34, 35, 43, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 Input- Synchronous Address Inputs used to select one of the 256K address locations . Sampled at the rising edge of the C...

Page 5 - Functional Overview

CY7C1364C Document #: 38-05689 Rev. *E Page 5 of 18 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock. The CY7C1364C supports secondary cache in s...

Page 6 - ZZ Mode Electrical Characteristics

CY7C1364C Document #: 38-05689 Rev. *E Page 6 of 18 Burst Sequences The CY7C1364C provides a two-bit wraparound counter, fedby A [1:0] , that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specif-ically to support Intel Pentium applications. The...

Page 7 - Truth Table

CY7C1364C Document #: 38-05689 Rev. *E Page 7 of 18 Truth Table [3, 4, 5, 6, 7, 8] Next Cycle Address Used ZZ CE 3 CE 2 CE 1 ADSP ADSC ADV OE DQ Write Unselected None L X X H X L X X Tri-State X Unselected None L H X L L X X X Tri-State X Unselected None L X L L L X X X Tri-State X Unselected None L...

Page 8 - Truth Table for Read/Write

CY7C1364C Document #: 38-05689 Rev. *E Page 8 of 18 Truth Table for Read/Write [3, 4] Function GW BWE BW D BW C BW B BW A Read H H X X X X Read H L H H H H Write Byte A – DQ A H L H H H L Write Byte B – DQ B H L H H L H Write Bytes B, A H L H H L L Write Byte C – DQ C H L H L H H Write Bytes C, A H ...

Page 9 - Electrical Characteristics

CY7C1364C Document #: 38-05689 Rev. *E Page 9 of 18 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature withPower Applied ..........................................

Page 10 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1364C Document #: 38-05689 Rev. *E Page 10 of 18 Capacitance [11] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5 pF C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resistance [11] Pa...

Page 11 - Switching Characteristics

CY7C1364C Document #: 38-05689 Rev. *E Page 11 of 18 Switching Characteristics Over the Operating Range [12,13] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t POWER V DD (Typical) to the First Access [14] 1 1 1 ms Clock t CYC Clock Cycle Time 4.0 5.0 6.0 ns t CH Clock HIGH...

Page 12 - Switching Waveforms; Read Cycle Timing

CY7C1364C Document #: 38-05689 Rev. *E Page 12 of 18 Switching Waveforms Read Cycle Timing [18] Note: 18. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t...

Page 13 - Write Cycle Timing

CY7C1364C Document #: 38-05689 Rev. *E Page 13 of 18 Write Cycle Timing [18,19] Note: 19. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW[A :D]...

Page 14 - Read/Write Cycle Timing

CY7C1364C Document #: 38-05689 Rev. *E Page 14 of 18 Read/Write Cycle Timing [18,20, 21] Notes: 20. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.21. GW is HIGH. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE AD...

Page 15 - ZZ Mode Timing; CLK

CY7C1364C Document #: 38-05689 Rev. *E Page 15 of 18 ZZ Mode Timing [22, 23] Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.23. DQs are in High-Z when exiting ZZ sleep mode. Switching Waveforms (conti...

Page 16 - Ordering Information

CY7C1364C Document #: 38-05689 Rev. *E Page 16 of 18 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part and Packag...

Page 17 - Package Diagram

CY7C1364C Document #: 38-05689 Rev. *E Page 17 of 18 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pro...

Page 18 - Document History Page; Issue Date

CY7C1364C Document #: 38-05689 Rev. *E Page 18 of 18 Document History Page Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAMDocument Number: 38-05689 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 286269 See ECN PCI New data sheet *A 320834 See ECN PCI Changed 225 MH...