Cypress CY7C1360C - Manuals

Cypress CY7C1360C – Manual in PDF format online.

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Manual

Manual Cypress CY7C1360C

Summary

Page 2 - Selection Guide; Unit

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 2 of 31 . Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA ADDRESSREGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BW...

Page 3 - Pin Configurations

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC/7 2 M NC/3 6 M V SS V DD NC/1 8 M A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP...

Page 6 - TMS

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable with JTAG) CY7C1360C (256K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE N...

Page 7 - Pin Definitions

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 7 of 31 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 [2] are samp...

Page 8 - Functional Overview

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 8 of 31 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. All data outputs pass throughoutput registers controlled by the rising edge of the clock.Maximum access delay from the clock...

Page 9 - ZZ Mode Electrical Characteristics

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 9 of 31 conducted, the data presented to the DQs is written into thecorresponding address location in the memory core. If a ByteWrite is conducted, only the selected bytes are written. Bytesnot selected during a Byte Write operation will remainuna...

Page 11 - Disabling the JTAG Feature; Truth Table for Read/Write; GW

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 11 of 31 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1360C/CY7C1362C incorporates a serial boundaryscan test access port (TAP) in the BGA package only. TheTQFP package does not offer this functionality. This partoperates in accordance with IEE...

Page 12 - TAP Controller Block Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register; ) when the BYPASS instruction is executed.; TAP Instruction Set; Overview

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 12 of 31 TAP Controller Block Diagram Performing a TAP Reset A RESET is performed by forcing TMS HIGH (V DD ) for five rising edges of TCK. This RESET does not affect the operationof the SRAM and may be performed while the SRAM isoperating. At pow...

Page 13 - BYPASS; TAP Timing; Test Clock

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 13 of 31 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded into the instruction register. It also places theinstruction register between the TDI and TDO balls and allowsthe IDCODE to be shifted out of the device when ...

Page 16 - 65-ball FBGA Boundary Scan Order

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 16 of 31 165-ball FBGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2 B7 GW 38 P6 A1 2 B7 GW...

Page 17 - 19-ball BGA Boundary Scan Order

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 17 of 31 119-ball BGA Boundary Scan Order CY7C1360C (256K x 36) CY7C1362C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 K4 CLK 37 P4 A0 1 K4 CLK 37 P4 A0 2 H4 GW 38 N4 A1 2 H4 GW ...

Page 18 - Electrical Characteristics

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 18 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ....................................

Page 19 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 19 of 31 Capacitance [16] Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5 5 5 pF C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Output...

Page 20 - Switching Characteristics

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 20 of 31 Switching Characteristics Over the Operating Range [17, 18] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t POWER V DD (Typical) to the First Access [19] 1 1 1 ms Clock t CYC Clock Cycle Time 4.0 5.0 6.0 ns t CH ...

Page 21 - Switching Waveforms; Read Cycle Timing

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 21 of 31 Switching Waveforms Read Cycle Timing [23] Note: 23. On this diagram, when CE is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ...

Page 22 - Write Cycle Timing

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 22 of 31 Write Cycle Timing [23, 24] Note: 24. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BW...

Page 23 - Read/Write Cycle Timing

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 23 of 31 Read/Write Cycle Timing [23, 25, 26] Notes: 25. The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC.26. GW is HIGH. Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ...

Page 24 - ZZ Mode Timing; CLK

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 24 of 31 ZZ Mode Timing [27, 28] Notes: 27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.28. DQs are in High-Z when exiting ZZ sleep mode. Switching Wavefor...

Page 25 - Ordering Information; Commercial

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 25 of 31 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part a...

Page 26 - visit

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 26 of 31 200 CY7C1360C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (3 Chip Enable) Commercial CY7C1362C-200AXC CY7C1360C-200AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) CY7C136...

Page 28 - Package Diagrams

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 28 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS...

Page 31 - Document History Page; Issue Date

CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 31 of 31 Document History Page Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAMDocument Number: 38-05540 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 241690 See ECN RKF New data sheet *A 278130 Se...