Cypress CY7C1360C - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit
- Page 3 – Pin Configurations
- Page 6 – TMS
- Page 7 – Pin Definitions
- Page 8 – Functional Overview
- Page 9 – ZZ Mode Electrical Characteristics
- Page 11 – Disabling the JTAG Feature; Truth Table for Read/Write; GW
- Page 12 – TAP Controller Block Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register; ) when the BYPASS instruction is executed.; TAP Instruction Set; Overview
- Page 13 – BYPASS; TAP Timing; Test Clock
- Page 16 – 65-ball FBGA Boundary Scan Order
- Page 17 – 19-ball BGA Boundary Scan Order
- Page 18 – Electrical Characteristics
- Page 19 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 20 – Switching Characteristics
- Page 21 – Switching Waveforms; Read Cycle Timing
- Page 22 – Write Cycle Timing
- Page 23 – Read/Write Cycle Timing
- Page 24 – ZZ Mode Timing; CLK
- Page 25 – Ordering Information; Commercial
- Page 26 – visit
- Page 28 – Package Diagrams
- Page 31 – Document History Page; Issue Date
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1360C
CY7C1362C
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05540 Rev. *H
Revised September 14, 2006
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O operation (V
DDQ
)
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
•
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
Functional Description
[1]
The CY7C1360C/CY7C1362C SRAM integrates 256K x 36
and 512K x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and
CE
3
[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1360C/CY7C1362C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
A0, A1, A
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
BW
B
BW
A
CE
1
DQ
B,
DQP
B
WRITE REGISTER
DQ
A,
DQP
A
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
2
MODE
CE2
CE3
GW
BWE
PIPELINED
ENABLE
DQs
DQP
A
DQP
B
OUTPUT
REGISTERS
INPUT
REGISTERS
E
DQ
A,
DQP
A
WRITE DRIVER
OUTPUT
BUFFERS
DQ
B,
DQP
B
WRITE DRIVER
A[1:0]
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1362C (512K x 18)
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Summary
CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 2 of 31 . Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA ADDRESSREGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BW...
CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC/7 2 M NC/3 6 M V SS V DD NC/1 8 M A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD ZZDQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP...
CY7C1360CCY7C1362C Document #: 38-05540 Rev. *H Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable with JTAG) CY7C1360C (256K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE N...
