Cypress CY7C1355C - Manuals

Cypress CY7C1355C – Manual in PDF format online.

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Manual

Manual Cypress CY7C1355C

Summary

Page 3 - Pin Configurations

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 3 of 28 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC /288M NC/144M V SS V DD NC/36M A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ...

Page 6 - TMS

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 6 of 28 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip enable with JTAG) CY7C1355C (256K x 36) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ D DQ D MODE NC ...

Page 7 - Pin Definitions

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 7 of 28 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW A , BW B BW C , BW D...

Page 8 - Functional Overview

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 8 of 28 Functional Overview The CY7C1355C/CY7C1357C is a synchronous flow-throughburst SRAM designed specifically to eliminate wait statesduring Write-Read transitions. All synchronous inputs passthrough input registers controlled by the rising ed...

Page 11 - Disabling the JTAG Feature; ) to prevent clocking of the device. TDI and TMS are; TAP Controller State Diagram; Performing a TAP Reset; Instruction Register

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 11 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355C/CY7C1357C incorporates a serial boundaryscan test access port (TAP) in the BGA package only. TheTQFP package does not offer this functionality. This partoperates in accordance with IEE...

Page 12 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 12 of 28 Diagram. Upon power-up, the instruction register is loadedwith the IDCODE instruction. It is also loaded with the IDCODEinstruction if the controller is placed in a reset state asdescribed in the previous section. When the TAP controller ...

Page 13 - Test Clock

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 13 of 28 TAP Timing TAP AC Switching Characteristics Over the Operating Range [10, 11] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH Time 20 ns t TL TCK Clock LOW T...

Page 15 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 15 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code D...

Page 16 - 19-ball BGA Boundary Scan Order

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 16 of 28 119-ball BGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball Id Signal Name Bit# ball Id Signal Name 1 K4 CLK 37 R6 A 1 K4 CLK 37 R6 A 2 H4 WE 38 T5 A 2 H4 WE 38 ...

Page 17 - 65-ball FBGA Boundary Scan Order

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 17 of 28 165-ball FBGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A 2 B7 WE 38 P4 A 2 B7 WE 38...

Page 18 - Electrical Characteristics

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 18 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ....................................

Page 19 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 19 of 28 Capacitance [15] Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V. V DDQ = 2.5V 5 5 5 pF C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Outpu...

Page 20 - Switching Characteristics

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 20 of 28 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –133 –100 Unit Min. Max. Min. Max. t POWER V DD (Typical) to the First Access [18] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 3.0 4.0 ns ...

Page 21 - Switching Waveforms

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 21 of 28 Switching Waveforms Read/Write Waveforms [22, 23, 24] Notes: 22. For this waveform ZZ is tied LOW.23. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 24. Order of th...

Page 22 - NOP, STALL and DESELECT Cycles

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 22 of 28 NOP, STALL and DESELECT Cycles [22, 23, 25] Note: 25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Switching Waveforms (continued) WRITE D(A1) 1 2...

Page 23 - ZZ Mode Timing; CLK

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 23 of 28 ZZ Mode Timing [26, 27] Notes: 26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.27. DQs are in high-Z when exiting ZZ sleep mode. Switching Waveforms (continued...

Page 24 - Ordering Information; Commercial

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 24 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part a...

Page 25 - Package Diagrams

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS...

Page 28 - Document History Page; Issue Date

CY7C1355CCY7C1357C Document #: 38-05539 Rev. *E Page 28 of 28 Document History Page Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05539 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 242032 See ECN RKF...