Cypress CY7C1354C - Manuals

Cypress CY7C1354C – Manual in PDF format online.

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Manual

Manual Cypress CY7C1354C

Summary

Page 2 - Selection Guide; Unit

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 2 of 28 A0, A1, A C MODE BW a BW b WE CE1CE2CE3 OE READ LOGIC DQsDQP a DQP b D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AN...

Page 3 - Pin Configurations

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 3 of 28 Pin Configurations A A A A A 1 A 0 V SS V DD A A A A A A V DDQ V SS DQb DQb DQb V SS V DDQ DQb DQb V SS NC V DD DQaDQa V DDQ V SS DQaDQa V SS V DDQ V DDQ V SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQdDQdDQd V SS V DDQ A A CE ...

Page 5 - TMS

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 5 of 28 Pin Configurations (continued) 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R TDO NC/576M NC/1G DQP c DQ c DQP d NC DQ d A CE 1 BW b CE 3 BW c CEN A CE2 DQ c DQ d DQ d MODE NC DQ c DQ c DQ d DQ d DQ d NC/36M NC/72M V DDQ BW d BW a CLK WE V SS ...

Page 6 - Pin Definitions

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 6 of 28 Pin Definitions Pin Name I/O Type Pin Description A0, A1A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the CLK. BW a ,BW b , BW c ,BW d , Input- Synchronous Byte Write Select...

Page 7 - Functional Overview

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 7 of 28 Functional Overview The CY7C1354C and CY7C1356C are synchronous-pipelinedBurst NoBL SRAMs designed specifically to eliminate waitstates during Write/Read transitions. All synchronous inputspass through input registers controlled by the ris...

Page 8 - ZZ Mode Electrical Characteristics

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 8 of 28 Because the CY7C1354C and CY7C1356C are common I/Odevices, data should not be driven into the device while theoutputs are active. The Output Enable (OE) can be deassertedHIGH before presenting data to the DQ and DQP (DQ a,b,c,d /DQP a,b,c,...

Page 10 - Disabling the JTAG Feature; through a pull-up resistor. TDO should be; TAP Controller State Diagram; Performing a TAP Reset; A RESET is performed by forcing TMS HIGH (V; TAP Registers; Instruction Register

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 10 of 28 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1354C/CY7C1356C incorporates a serial boundaryscan test access port (TAP) in the BGA package only. TheTQFP package does not offer this functionality. This partoperates in accordance with IEE...

Page 11 - ) when the BYPASS instruction is executed.; TAP Instruction Set; and t

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 11 of 28 TDI and TDO balls as shown in the Tap Controller BlockDiagram. Upon power-up, the instruction register is loadedwith the IDCODE instruction. It is also loaded with the IDCODEinstruction if the controller is placed in a reset state asdescr...

Page 12 - TAP Timing; Test Clock

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 12 of 28 PRELOAD allows an initial data pattern to be placed at thelatched parallel outputs of the boundary scan register cellsprior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phasesca...

Page 14 - Scan Register Sizes; Register Name; Identification Codes; Instruction

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 14 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code D...

Page 17 - Electrical Characteristics

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 17 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ....................................

Page 18 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 18 of 28 Capacitance [16] Parameter Description Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 5 5 5 pF C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Outp...

Page 19 - Switching Characteristics

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 19 of 28 Switching Characteristics Over the Operating Range [18, 19] Parameter Description –250 –200 –166 Unit Min. Max. Min. Max. Min. Max. t Power [17] V CC (typical) to the First Access Read or Write 1 1 1 ms Clock t CYC Clock Cycle Time 4.0 5 ...

Page 20 - Switching Waveforms

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 20 of 28 Switching Waveforms Read/Write Timing [23, 24, 25] Notes: 23. For this waveform ZZ is tied low.24. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 25. Order of the B...

Page 21 - NOP,STALL and DESELECT Cycles

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 21 of 28 NOP,STALL and DESELECT Cycles [23, 24, 26] Note: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. Switching Waveforms (continued) READ Q(A3) 4 5 6...

Page 22 - ZZ Mode Timing

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 22 of 28 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.28. I/Os are in High-Z when exiting ZZ sleep mode. ZZ Mode Timing [27, 28] Switching Waveforms (con...

Page 23 - Ordering Information; Commercial

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 23 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part a...

Page 24 - visit

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 24 of 28 250 CY7C1354C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356C-250AXC CY7C1354C-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356C-250BGC CY7C1354C-250BGXC 51-85115 119-ball ...

Page 25 - Package Diagrams

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS...

Page 28 - Document History Page; Issue Date

CY7C1354CCY7C1356C Document #: 38-05538 Rev. *G Page 28 of 28 Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05538 REV. ECN No. Issue Date Orig. of Change Description of Change ** 242032 See ECN RKF New...