Cypress CY7C1353G - Manuals

Page 2 - Selection Guide; Unit; Pin Configuration

CY7C1353G Document #: 38-05515 Rev. *E Page 2 of 13 Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100-Pin TQFP Pinout A A A A A1 A0 NC/28 8M NC/ 14 4M V SS V DD NC/36M A A A A A A ANCNC...

Page 3 - Pin Definitions

CY7C1353G Document #: 38-05515 Rev. *E Page 3 of 13 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the 256K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW [A:B] Input- Synchronous ...

Page 4 - Functional Overview; Single Read Accesses

CY7C1353G Document #: 38-05515 Rev. *E Page 4 of 13 Functional Overview The CY7C1353G is a synchronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock....

Page 5 - Interleaved Burst Address Table; ZZ Mode Electrical Characteristics

CY7C1353G Document #: 38-05515 Rev. *E Page 5 of 13 Linear Burst Address Table (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Address Table (MODE = Floating or V DD ) First Address A...

Page 6 - Partial Truth Table for Read/Write; Function

CY7C1353G Document #: 38-05515 Rev. *E Page 6 of 13 Partial Truth Table for Read/Write [2, 3, 9] Function WE BW A BW B Read H X X Write – No bytes written L H H Write Byte A – (DQ A and DQP A ) L L H Write Byte B – (DQ B and DQP B ) L H L Write All Bytes L L L Note: 9. Table only lists a partial lis...

Page 7 - Electrical Characteristics

CY7C1353G Document #: 38-05515 Rev. *E Page 7 of 13 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Applied ......................

Page 9 - Switching Characteristics

CY7C1353G Document #: 38-05515 Rev. *E Page 9 of 13 Switching Characteristics Over the Operating Range [17, 18] Parameter Description –133 –100 Unit Min Max Min Max t POWER V DD (Typical) to the first Access [13] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t CL Clock LOW...

Page 10 - Switching Waveforms

CY7C1353G Document #: 38-05515 Rev. *E Page 10 of 13 Switching Waveforms Read/Write Waveforms [19, 20, 21] Notes: 19.For this waveform ZZ is tied low.20.When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 21.Order of the Burst sequ...

Page 11 - NOP, STALL and DESELECT Cycles; ZZ Mode Timing

CY7C1353G Document #: 38-05515 Rev. *E Page 11 of 13 NOP, STALL and DESELECT Cycles [19, 20, 22] ZZ Mode Timing [23,24] Notes: 22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.23.Device must be deselected when ...

Page 13 - Document History Page; Issue Date

CY7C1353G Document #: 38-05515 Rev. *E Page 13 of 13 Document History Page Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05515 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 224363 See ECN RKF New data sheet *A 288431 See...