Cypress CY7C1352G - Manuals

Page 2 - Selection Guide; Unit; Pin Configuration

CY7C1352G Document #: 38-05514 Rev. *D Page 2 of 12 Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA Pin Configuration A A A A A 1 A 0 NC/2 88M NC /144M V SS V DD N C /...

Page 3 - Pin Definitions

CY7C1352G Document #: 38-05514 Rev. *D Page 3 of 12 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 256K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW [A:B] Input- Synchronous Byt...

Page 4 - Functional Overview; Single Read Accesses

CY7C1352G Document #: 38-05514 Rev. *D Page 4 of 12 Functional Overview The CY7C1352G is a synchronous-pipelined Burst SRAMdesigned specifically to eliminate wait states duringWrite/Read transitions. All synchronous inputs pass throughinput registers controlled by the rising edge of the clock. Thecl...

Page 5 - ZZ Mode Electrical Characteristics

CY7C1352G Document #: 38-05514 Rev. *D Page 5 of 12 Interleaved Burst Address Table (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A...

Page 6 - Electrical Characteristics

CY7C1352G Document #: 38-05514 Rev. *D Page 6 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ..................................... − 65°C to +150°C Ambient Temperature withPower Applied .........................................

Page 8 - Switching Characteristics

CY7C1352G Document #: 38-05514 Rev. *D Page 8 of 12 Switching Characteristics Over the Operating Range [16, 17] Parameter Description –250 –200 –166 –133 Unit Min. Max. Min. Max. Min. Max. Min. Max. t POWER V DD (typical) to the first Access [12] 1 1 1 1 ms Clock t CYC Clock Cycle Time 4.0 5.0 6.0 7...

Page 9 - Switching Waveforms

CY7C1352G Document #: 38-05514 Rev. *D Page 9 of 12 Switching Waveforms Read/Write Timing [18, 19, 20] Notes: 18. For this waveform ZZ is tied low.19. When CE is LOW: CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 20. Order of the Burst seque...

Page 10 - ZZ Mode Timing; CLK

CY7C1352G Document #: 38-05514 Rev. *D Page 10 of 12 NOP, STALL, and DESELECT Cycles [18, 19, 21] ZZ Mode Timing [22, 23] Notes: 21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.22. Device must be deselected w...

Page 12 - Document History Page; Issue

CY7C1352G Document #: 38-05514 Rev. *D Page 12 of 12 Document History Page Document Title: CY7C1352G 4-Mbit (256K x 18) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05514 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 224362 See ECN RKF New data sheet *A 288431 See ECN...