Cypress CY7C1345G - Manuals

Cypress CY7C1345G – Manual in PDF format online.

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Manual

Manual Cypress CY7C1345G

Summary

Page 2 - Logic Block Diagram

CY7C1345G Document Number: 38-05517 Rev. *E Page 2 of 20 Logic Block Diagram ADDRESSREGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A 0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 ...

Page 3 - Pin Configurations

CY7C1345G Document Number: 38-05517 Rev. *E Page 3 of 20 Pin Configurations 100-Pin TQFP Pinout A A A A A 1 A 0 NC/7 2M NC/36M V SS V DD NC/9M A A A A A A DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP ...

Page 5 - Pin Definitions

CY7C1345G Document Number: 38-05517 Rev. *E Page 5 of 20 Pin Definitions Name IO Description A0, A1, A Input Synchronous Address Inputs Used to Select One of the 128K Address Locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled activ...

Page 6 - Functional Overview; Single Read Accesses; Single Write Accesses Initiated by ADSP

CY7C1345G Document Number: 38-05517 Rev. *E Page 6 of 20 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 6.5 ns (133 MHz device). The CY7C1345G supports secondary cache in systems ...

Page 7 - ZZ Mode Electrical Characteristics

CY7C1345G Document Number: 38-05517 Rev. *E Page 7 of 20 Burst Sequences The CY7C1345G provides an on-chip two-bit wrap around burst counter inside the SRAM. The burst counter is fed by A [1:0] and follows either a linear or interleaved burst order. The burst order is determined by the state of the ...

Page 8 - Truth Table

CY7C1345G Document Number: 38-05517 Rev. *E Page 8 of 20 Truth Table The truth table for CY7C1345G follows. [1, 2, 3, 4, 5] Cycle Description Address Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power down None H X X L X L X X X L-H Tri-State Deselected Cycle, Power down No...

Page 9 - Truth Table for Read or Write; The partial truth table for read or write follows.

CY7C1345G Document Number: 38-05517 Rev. *E Page 9 of 20 Truth Table for Read or Write The partial truth table for read or write follows. [1, 6] Function GW BWE BW D BW C BW B BW A Read H H X X X X Read H L H H H H Write Byte (A, DQP A ) H L H H H L Write Byte (B, DQP B ) H L H H L H Write Bytes (B,...

Page 10 - Electrical Characteristics

CY7C1345G Document Number: 38-05517 Rev. *E Page 10 of 20 Maximum Ratings Exceeding the maximum ratings may shorten the battery life of the device. These user guidelines are not tested.Storage Temperature ................................. –65°C to +150°CAmbient Temperature with Power Applied ..........

Page 11 - AC Test Loads and Waveforms

CY7C1345G Document Number: 38-05517 Rev. *E Page 11 of 20 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions 100 TQFP Max 119 BGA Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V. V DDQ = 3.3...

Page 12 - Switching Characteristics

CY7C1345G Document Number: 38-05517 Rev. *E Page 12 of 20 Switching Characteristics Over the Operating Range [9, 10] Parameter Description –133 –100 Unit Min Max Min Max t POWER V DD (Typical) to the first Access [11] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t CL Cloc...

Page 13 - Timing Diagrams; Figure 1; Figure 1. Read Cycle Timing

CY7C1345G Document Number: 38-05517 Rev. *E Page 13 of 20 Timing Diagrams Figure 1 shows the read cycle timing. [15] Figure 1. Read Cycle Timing tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 t CEH tCES Data Out (Q) High-Z t CLZ tDOH tCDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst...

Page 14 - Figure 2. Write Cycle Timing

CY7C1345G Document Number: 38-05517 Rev. *E Page 14 of 20 Figure 2 shows the write cycle timing. [15, 16] Figure 2. Write Cycle Timing Timing Diagrams (continued) t CYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) ...

Page 16 - Figure 4. ZZ Mode Timing

CY7C1345G Document Number: 38-05517 Rev. *E Page 16 of 20 Figure 4 shows the ZZ mode timing. [19, 20] Figure 4. ZZ Mode Timing Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes: 19. Device mu...

Page 17 - Ordering Information; for actual products offered.

CY7C1345G Document Number: 38-05517 Rev. *E Page 17 of 20 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram Part and P...

Page 18 - Package Diagrams

CY7C1345G Document Number: 38-05517 Rev. *E Page 18 of 20 Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in ...

Page 20 - Document History Page; Change

Document Number: 38-05517 Rev. *E Revised July 15, 2007 Page 20 of 20 Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders . CY7C1345G © Cypress Semiconduct...