Cypress CY7C1345G - Manual
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Table of Contents:
- Page 2 – Logic Block Diagram
- Page 3 – Pin Configurations
- Page 5 – Pin Definitions
- Page 6 – Functional Overview; Single Read Accesses; Single Write Accesses Initiated by ADSP
- Page 7 – ZZ Mode Electrical Characteristics
- Page 8 – Truth Table
- Page 9 – Truth Table for Read or Write; The partial truth table for read or write follows.
- Page 10 – Electrical Characteristics
- Page 11 – AC Test Loads and Waveforms
- Page 12 – Switching Characteristics
- Page 13 – Timing Diagrams; Figure 1; Figure 1. Read Cycle Timing
- Page 14 – Figure 2. Write Cycle Timing
- Page 16 – Figure 4. ZZ Mode Timing
- Page 17 – Ordering Information; for actual products offered.
- Page 18 – Package Diagrams
- Page 20 – Document History Page; Change
CY7C1345G
4-Mbit (128K x 36) Flow Through Sync SRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 38-05517 Rev. *E
Revised July 15, 2007
Features
■
128K x 36 common IO
■
3.3V core power supply (V
DD
)
■
2.5V or 3.3V IO supply (V
DDQ
)
■
Fast clock-to-output times
❐
6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium inter-
leaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
Available in Pb-free 100-Pin TQFP package, Pb-free and
non-Pb-free 119-Ball BGA package
■
ZZ Sleep Mode option
Functional Description
The CY7C1345G is a 128K x 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 6.5 ns (133 MHz version). A two-bit on-chip counter captures
the first address in a burst and increments the address automat-
ically for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive edge triggered Clock
Input (CLK). The synchronous inputs include all addresses, all
data inputs, address pipelining Chip Enable (CE
1
), depth
expansion Chip Enables (CE
2
and
CE
3
), Burst Control inputs
(ADSC, ADSP, and ADV), Write Enables (BW
x
, and BWE), and
Global Write (GW). Asynchronous inputs include the Output
Enable (OE) and the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3V core power supply
while all outputs operate with either a +2.5 or +3.3V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
For best practice recommendations, refer to the Cypress appli-
cation note
AN1064, SRAM System Guidelines
Selection Guide
Parameter
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.0
ns
Maximum Operating Current
225
205
mA
Maximum Standby Current
40
40
mA
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Summary
CY7C1345G Document Number: 38-05517 Rev. *E Page 2 of 20 Logic Block Diagram ADDRESSREGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A 0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 ...
CY7C1345G Document Number: 38-05517 Rev. *E Page 3 of 20 Pin Configurations 100-Pin TQFP Pinout A A A A A 1 A 0 NC/7 2M NC/36M V SS V DD NC/9M A A A A A A DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NCV DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP ...
CY7C1345G Document Number: 38-05517 Rev. *E Page 5 of 20 Pin Definitions Name IO Description A0, A1, A Input Synchronous Address Inputs Used to Select One of the 128K Address Locations . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled activ...
