Cypress CY7C1334H - Manuals

Page 2 - Selection Guide; Unit; Pin Configuration

CY7C1334H Document #: 38-05678 Rev. *B Page 2 of 13 . Selection Guide 166 MHz 133 MHz Unit Maximum Access Time (t CO ) 3.5 4.0 ns Maximum Operating Current (I DD ) 240 225 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration A A A A A 1 A 0 NC/288M NC/144M V SS V DD NC/36M A A A A A NC/4M NC D...

Page 3 - Pin Definitions

CY7C1334H Document #: 38-05678 Rev. *B Page 3 of 13 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 64K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW [A:D] Input- Synchronous Byte...

Page 4 - Functional Overview; Single Read Accesses

CY7C1334H Document #: 38-05678 Rev. *B Page 4 of 13 Functional Overview The CY7C1334H is a synchronous-pipelined Burst SRAMdesigned specifically to eliminate wait states duringWrite/Read transitions. All synchronous inputs pass throughinput registers controlled by the rising edge of the clock. Thecl...

Page 5 - DD; Cycle Description Truth Table

CY7C1334H Document #: 38-05678 Rev. *B Page 5 of 13 Interleaved Burst Address Table (MODE = Floating or V DD ) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A...

Page 7 - Electrical Characteristics

CY7C1334H Document #: 38-05678 Rev. *B Page 7 of 13 Maximum Rating (Above which the useful life may be impaired. For user guide-lines not tested.) Storage Temperature ..................................... − 65°C to +150°C Ambient Temperature withPower Applied ...........................................

Page 8 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1334H Document #: 38-05678 Rev. *B Page 8 of 13 Capacitance [11] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V, V DDQ = 2.5V 5 pF C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resistance [11] Pa...

Page 9 - Switching Characteristics

CY7C1334H Document #: 38-05678 Rev. *B Page 9 of 13 Switching Characteristics Over the Operating Range [12, 13] 166 MHz 133 MHz Parameter Description Min. Max. Min. Max. Unit t POWER V DD (typical) to the First Access [14] 1 1 ms Clock t CYC Clock Cycle Time 6.0 7.5 ns t CH Clock HIGH 2.5 3.0 ns t C...

Page 10 - Switching Waveforms

CY7C1334H Document #: 38-05678 Rev. *B Page 10 of 13 Switching Waveforms Read/Write Timing [18, 19, 20] Notes: 18. For this waveform ZZ is tied LOW.19. When CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 20. Order of the Burst sequ...

Page 11 - ZZ Mode Timing; CLK

CY7C1334H Document #: 38-05678 Rev. *B Page 11 of 13 NOP, STALL, and Deselect Cycles [18, 19, 21] ZZ Mode Timing [22, 23] Notes: 21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.22. Device must be deselected w...

Page 12 - Ordering Information; Commercial; Package Diagram

CY7C1334H Document #: 38-05678 Rev. *B Page 12 of 13 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pro...

Page 13 - Document History Page; Issue Date

CY7C1334H Document #: 38-05678 Rev. *B Page 13 of 13 Document History Page Document Title: CY7C1334H 2-Mbit (64K x 32) Pipelined SRAM with NoBL™ ArchitectureDocument Number: 38-05678 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 347357 See ECN PCI New Data Sheet *A 424820 See ECN ...