Cypress CY7C1334H - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit; Pin Configuration
- Page 3 – Pin Definitions
- Page 4 – Functional Overview; Single Read Accesses
- Page 5 – DD; Cycle Description Truth Table
- Page 7 – Electrical Characteristics
- Page 8 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 9 – Switching Characteristics
- Page 10 – Switching Waveforms
- Page 11 – ZZ Mode Timing; CLK
- Page 12 – Ordering Information; Commercial; Package Diagram
- Page 13 – Document History Page; Issue Date
2-Mbit (64K x 32) Pipelined SRAM with
NoBL™ Architecture
CY7C1334H
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05678 Rev. *B
Revised February 6, 2006
Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed write
• Asynchronous output enable (OE)
• Offered in Lead-Free JEDEC-standard 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
Functional Description
[1]
The CY7C1334H is a 3.3V/2.5V, 64K x 32
synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1334H is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of the SRAM, especially
in systems that require frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
[A:D]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
A0, A1, A
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
C
BW
D
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram
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Summary
CY7C1334H Document #: 38-05678 Rev. *B Page 2 of 13 . Selection Guide 166 MHz 133 MHz Unit Maximum Access Time (t CO ) 3.5 4.0 ns Maximum Operating Current (I DD ) 240 225 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration A A A A A 1 A 0 NC/288M NC/144M V SS V DD NC/36M A A A A A NC/4M NC D...
CY7C1334H Document #: 38-05678 Rev. *B Page 3 of 13 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 64K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter. BW [A:D] Input- Synchronous Byte...
CY7C1334H Document #: 38-05678 Rev. *B Page 4 of 13 Functional Overview The CY7C1334H is a synchronous-pipelined Burst SRAMdesigned specifically to eliminate wait states duringWrite/Read transitions. All synchronous inputs pass throughinput registers controlled by the rising edge of the clock. Thecl...
