Cypress CY7C1330AV25 - Manuals

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Manual

Manual Cypress CY7C1330AV25

Summary

Page 2 - PRELIMINARY; Selection Guide; Unit; Pin Configurations

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 2 of 19 Selection Guide CY7C1330AV25-250CY7C1332AV25-250 CY7C1330AV25-200 CY7C1332AV25- 200 Unit Maximum Access Time 2.0 2.25 ns Maximum Operating Current 600 550 mA Maximum CMOS Standby Current 280 260 mA Pin Configurations 2 ...

Page 3 - Pin Definitions

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 3 of 19 Pin Definitions Name I/O Type Description A Input- Synchronous Address Inputs used to select one of the address locations . Sampled at the rising edge of the K. BWS a BWS b BWS c BWS d Input- Synchronous Byte Write Sele...

Page 4 - Introduction; Functional Overview; Pipelined Read Accesses; Sleep Mode

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 4 of 19 Introduction Functional Overview The CY7C1330AV25 and CY7C1332AV25 are synchronous-pipelined Late Write SRAMs running at speeds up to 250 MHz.All synchronous inputs pass through input registers controlledby the rising e...

Page 5 - Cycle Description Truth Table

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 5 of 19 guaranteed. The device must be deselected prior to enteringthe “sleep” mode. CE must remain inactive for the duration oft ZZREC after the ZZ input returns LOW. Cycle Description Truth Table [1, 2, 3, 4, 5] Operation Add...

Page 6 - Instruction Register; ) when the BYPASS instruction is executed.

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 6 of 19 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This port operates in accor-dance with IEEE Standard 1149.1-1900 but does not have theset...

Page 7 - EXTEST; BYPASS

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 7 of 19 EXTEST EXTEST is a mandatory 1149.1 instruction which is to beexecuted whenever the instruction register is loaded with all0s. EXTEST is not implemented in this SRAM TAP controller,and therefore this device is not compl...

Page 8 - TAP Controller State Diagram

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 8 of 19 Note: 6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. TAP Controller State Diagram [6] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UP...

Page 9 - TAP Controller Block Diagram

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 9 of 19 TAP Controller Block Diagram TAP Electrical Characteristics Over the Operating Range [7, 8, 9] Parameter Description Test Conditions Min. Max. Unit V OH1 Output HIGH Voltage I OH = − 2.0 mA 1.7 V V OH2 Output HIGH Volta...

Page 10 - TAP Timing and Test Conditions; Test Clock; Identification Register Definitions

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 10 of 19 t CH Capture Hold after Clock Rise 5 ns Output Times t TDOV TCK Clock LOW to TDO Valid 10 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions [11] TAP AC Switching Characteristics Over the Operat...

Page 11 - Scan Register Sizes

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 11 of 19 Scan Register Sizes Register Name Bit Size—CY7C1330AV25 Bit Size—CY7C1332AV25 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 70 51 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ...

Page 12 - Bump ID

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 12 of 19 Boundary Scan Order (512K x 36) Bit # Bump ID Bit # Bump ID Bit # Bump ID 1 5R 25 6F 49 2H 2 4P 26 7E 50 1H 3 4T 27 6E 51 3G 4 6R 28 7D 52 4D 5 5T 29 6D 53 4E 6 7T 30 6A 54 4G 7 6P 31 6C 55 4H 8 7P 32 5C 56 4M 9 6N 33 ...

Page 13 - Maximum Ratings; Electrical Characteristics

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 13 of 19 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ................

Page 14 - AC Test Loads and Waveforms; Capacitance; Thermal Resistance

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 14 of 19 AC Test Loads and Waveforms Notes: 17. Tested initially and after any design or process change that may affect these parameters.18. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timin...

Page 15 - Switching Characteristics

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 15 of 19 Switching Characteristics [18, 19, 20, 21] Parameter Description 250 200 Unit Min. Max. Min. Max. t Power V CC (typical) to the First Access Read or Write [22] 1 1 ms Clock t CYC Clock Cycle Time 4.0 5.0 ns F MAX Maxim...

Page 16 - Switching Waveforms; ADDRESS

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 16 of 19 Switching Waveforms READ/WRITE/DESELECT Sequence (OE Controlled) [23, 24, 25, 26] Notes: 23. The combination of WE and BWS x (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Descripti...

Page 17 - CLK

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 17 of 19 READ/WRITE/DESELECT Sequence (CE Controlled) Switching Waveforms (continued) CLK CE t CYC t CH t CL t CES t CEH = DON’T CARE = UNDEFINED READ WRI T E READ DESEL ECT WRITE De s e lect RE AD WRI T E WRI T E DES E LECT AD...

Page 18 - Ordering Information; Commercial; Package Diagram

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 18 of 19 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circui...

Page 19 - Document History Page; Issue Date

PRELIMINARY CY7C1330AV25CY7C1332AV25 Document No: 001-07844 Rev. *A Page 19 of 19 Document History Page Document Title: CY7C1330AV25/CY7C1332AV25 18-Mbit (512K x 36/1Mbit x 18)Pipelined Register-Register Late Write SRAMDocument Number: 001-07844 REV. ECN No. Issue Date Orig. of Change Description of...