Cypress CY7C1305BV25 - Manuals

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Manual

Manual Cypress CY7C1305BV25

Summary

Page 2 - Selection Guide; Unit; Maximum Operating Frequency; Array

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 2 of 21 Selection Guide CY7C1305BV25-167CY7C1307BV25-167 Unit Maximum Operating Frequency 167 MHz Maximum Operating Current 400 mA 256Kx1 8 Array CLK A [17:0] Gen. K K ControlLogic Address Register D [17:0] Read Add . Deco de Read Data Reg....

Page 3 - Pin Configuration

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 3 of 21 \ Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1305BV25 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A NC GND/ 144M NC/ 36M WPS BWS 1 K NC RPS A GND/ 72M NC B NC Q9 D9 A NC K BWS 0 A NC NC Q8 C NC NC D10 VSS A NC A VSS NC Q7 D...

Page 4 - Pin Definitions

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 4 of 21 Pin Definitions Name I/O Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations . CY7C1305BV25 – D [17:0] CY7C1307BV25 – D [35:0] WPS Input- Synchronous ...

Page 5 - Introduction

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 5 of 21 Introduction Functional Overview The CY7C1305BV25/CY7C1307BV25 are synchronouspipelined Burst SRAMs equipped with both a Read port and aWrite port. The Read port is dedicated to Read operations andthe Write Port is dedicated to Writ...

Page 6 - Byte Write Operations; and BWS; Single Clock Mode; to allow the SRAM to adjust its; Application Example

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 6 of 21 When deselected, the write port will ignore all inputs after thepending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1305BV25.A write operation is initiated as described ...

Page 7 - Truth Table

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 7 of 21 Truth Table [2, 3, 4, 5, 6, 7, 8, 9] Operation K RPS WPS DQ DQ DQ DQ Write Cycle : Load address on the rising edge of K; wait one cycle; input write data on two consecutive K and K rising edges. L-H H [8] L [9] D(A+00) at K(t+1) ↑ D...

Page 8 - Write Cycle Descriptions; BWS

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 8 of 21 Write Cycle Descriptions (CY7C1307BV25) [2, 10 ] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L-H – During the Data portion of a Write sequence, all four bytes (D [35:0] ) are written into the device. L L L L – L-H During the Data p...

Page 9 - A Reset is performed by forcing TMS HIGH (V; Instruction Register; ) when the BYPASS instruction is executed.

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 9 of 21 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliantwith IEEE Standard #1149.1-1900. The TAP operates usingJEDEC standard 2.5V...

Page 10 - BYPASS

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 10 of 21 is loaded into the instruction register upon power-up orwhenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan registerto be connected between the TDI and TDO pins ...

Page 11 - TAP Controller State Diagram

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 11 of 21 TAP Controller State Diagram [11] Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SE...

Page 13 - Test Clock

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 13 of 21 Output Times t TDOV TCK Clock LOW to TDO Valid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions [14] Identification Register Definitions Instruction Field Value Description CY7C1305BV25 CY7C1307BV25 Rev...

Page 14 - Scan Register Sizes; Register Name; Instruction Codes; Instruction

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 14 of 21 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the ...

Page 15 - Boundary Scan Order; Bump ID; Internal

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 15 of 21 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 6...

Page 16 - Electrical Characteristics

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 16 of 21 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................ –65°C to + 150°C Ambient Temperature withPower Applied ............................................ –55°C to + 125°...

Page 17 - Capacitance; Parameter; AC Test Loads and Waveforms

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 17 of 21 Capacitance [22] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 2.5V. V DDQ = 1.5V 5 pF C CLK Clock Input Capacitance 6 pF C O Output Capacitance 7 pF AC Test Loads and Waveform...

Page 18 - Switching Characteristics

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 18 of 21 Switching Characteristics Over the Operating Range [23] Cypress Parameter Consortium Parameter Description 167 MHz Unit Min. Max. t Power [24] V CC (typical) to the First Access Read or Write 10 µ s Cycle Time t CYC t KHKH K Clock ...

Page 19 - Switching Waveforms; RPS

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 19 of 21 Switching Waveforms [27, 28, 29] Notes: 27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.28. Outputs are disabled (High-Z) one clock cycle after a NOP.29. ...

Page 20 - Quad Data Rate SRAM and QDR; Ordering Information; Commercial; Package Diagram

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 20 of 21 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied ...

Page 21 - Document History Page; Issue Date

CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 21 of 21 Document History Page Document Title: CY7C1305BV25/CY7C1307BV25 18-Mbit Burst of Four Pipelined SRAM with QDR™ ArchitectureDocument Number: 38-05630 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 253049 See ECN SY...