Cypress CY7C1305BV25 - Manual
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Table of Contents:
- Page 2 – Selection Guide; Unit; Maximum Operating Frequency; Array
- Page 3 – Pin Configuration
- Page 4 – Pin Definitions
- Page 5 – Introduction
- Page 6 – Byte Write Operations; and BWS; Single Clock Mode; to allow the SRAM to adjust its; Application Example
- Page 7 – Truth Table
- Page 8 – Write Cycle Descriptions; BWS
- Page 9 – A Reset is performed by forcing TMS HIGH (V; Instruction Register; ) when the BYPASS instruction is executed.
- Page 10 – BYPASS
- Page 11 – TAP Controller State Diagram
- Page 13 – Test Clock
- Page 14 – Scan Register Sizes; Register Name; Instruction Codes; Instruction
- Page 15 – Boundary Scan Order; Bump ID; Internal
- Page 16 – Electrical Characteristics
- Page 17 – Capacitance; Parameter; AC Test Loads and Waveforms
- Page 18 – Switching Characteristics
- Page 19 – Switching Waveforms; RPS
- Page 20 – Quad Data Rate SRAM and QDR; Ordering Information; Commercial; Package Diagram
- Page 21 – Document History Page; Issue Date
18-Mbit Burst of 4 Pipelined SRAM with
QDR™ Architecture
CY7C1307BV25
CY7C1305BV25
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05630 Rev. *A
Revised April 3, 2006
Features
• Separate independent Read and Write data ports
• Supports concurrent transactions
• 167-MHz clock for high bandwidth
• 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
• SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG interface
Configurations
• CY7C1305BV25 – 1M x 18
• CY7C1307BV25 – 512K x 36
Functional Description
The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305BV25) and four
36-bit words (CY7C1307BV25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Summary
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 2 of 21 Selection Guide CY7C1305BV25-167CY7C1307BV25-167 Unit Maximum Operating Frequency 167 MHz Maximum Operating Current 400 mA 256Kx1 8 Array CLK A [17:0] Gen. K K ControlLogic Address Register D [17:0] Read Add . Deco de Read Data Reg....
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 3 of 21 \ Pin Configuration 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1305BV25 (1M x 18) 1 2 3 4 5 6 7 8 9 10 11 A NC GND/ 144M NC/ 36M WPS BWS 1 K NC RPS A GND/ 72M NC B NC Q9 D9 A NC K BWS 0 A NC NC Q8 C NC NC D10 VSS A NC A VSS NC Q7 D...
CY7C1307BV25 CY7C1305BV25 Document #: 38-05630 Rev. *A Page 4 of 21 Pin Definitions Name I/O Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations . CY7C1305BV25 – D [17:0] CY7C1307BV25 – D [35:0] WPS Input- Synchronous ...
