Cypress CY7C1302DV25 - Manuals

Page 3 - Introduction; Pin Definitions

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 3 of 18 Introduction Functional Overview The CY7C1302DV25 is a synchronous pipelined Burst SRAMequipped with both a Read port and a Write port. The Readport is dedicated to Read operations and the Write port isdedicated to Write operations. Data flows i...

Page 4 - Application Example

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 4 of 18 Synchronous internal circuitry will automatically three-statethe outputs following the next rising edge of the positive outputclock (C). This will allow for a seamless transition betweendevices without the insertion of wait states in a depthexpa...

Page 6 - A Reset is performed by forcing TMS HIGH (V; Instruction Register; ) when the BYPASS instruction is executed.

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 6 of 18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliantwith IEEE Standard #1149.1-1900. The TAP operates usingJEDEC standard 2.5V I/O logic le...

Page 7 - BYPASS

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 7 of 18 is loaded into the instruction register upon power-up orwhenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan registerto be connected between the TDI and TDO pins when the TAPco...

Page 8 - TAP Controller State Diagram

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 8 of 18 TAP Controller State Diagram [9] Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SELECTIR-SCAN CAPT...

Page 10 - TDO; Test Clock; ALL INPUT PULSES

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 10 of 18 Output Times t TDOV TCK Clock LOW to TDO Valid 20 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions [12] Identification Register Definitions Instruction Field Value Description CY7C1302DV25 Revision Number (31:29) 000 V...

Page 11 - Scan Register Sizes; Register Name; Instruction Codes; Instruction

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 11 of 18 Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID cod...

Page 12 - Boundary Scan Order; Bump ID; Internal

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 12 of 18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 ...

Page 13 - Electrical Characteristics

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 13 of 18 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to + 150°C Ambient Temperature withPower Applied ............................................ –55°C to + 125°C Supply Vol...

Page 14 - OUTPUT; OUTPUT

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 14 of 18 Thermal Resistance [20] Parameter Description Test Conditions 165 FBGA Package Unit Θ JA Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 16.7 ...

Page 15 - Switching Characteristics

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 15 of 18 Output Times t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns t DOH t CHQX Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns t CHZ t CHZ Clock (C and C) Rise to High-Z (Active to High-Z) [23, 24...

Page 16 - Switching Waveforms; RPS

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 16 of 18 Switching Waveforms [25, 26, 27] Notes: 25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.26. Outputs are disabled (High-Z) one clock cycle after a NOP.27. In this exampl...

Page 17 - Ordering Information; Commercial; Package Diagram

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 17 of 18 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress ...

Page 18 - Document History Page; Issue Date

CY7C1302DV25 Document #: 38-05625 Rev. *A Page 18 of 18 Document History Page Document Title:CY7C1302DV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ ArchitectureDocument Number: 38-05625 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 253010 See ECN SYT New Data Sheet *A 436864 See EC...