Cypress CY7C1302DV25 - Manual
Cypress CY7C1302DV25 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.
Table of Contents:
- Page 3 – Introduction; Pin Definitions
- Page 4 – Application Example
- Page 6 – A Reset is performed by forcing TMS HIGH (V; Instruction Register; ) when the BYPASS instruction is executed.
- Page 7 – BYPASS
- Page 8 – TAP Controller State Diagram
- Page 10 – TDO; Test Clock; ALL INPUT PULSES
- Page 11 – Scan Register Sizes; Register Name; Instruction Codes; Instruction
- Page 12 – Boundary Scan Order; Bump ID; Internal
- Page 13 – Electrical Characteristics
- Page 14 – OUTPUT; OUTPUT
- Page 15 – Switching Characteristics
- Page 16 – Switching Waveforms; RPS
- Page 17 – Ordering Information; Commercial; Package Diagram
- Page 18 – Document History Page; Issue Date
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
CY7C1302DV25
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05625 Rev. *A
Revised March 23, 2006
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Configurations
CY7C1302DV25 – 512K x 18
Functional Description
The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated data outputs to support Read operations
and the Write Port has dedicated data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of K clock. QDR has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K) and out of the device on every rising
edge of the output clock (C and C, or K and K in a single clock
domain) thereby maximizing performance while simplifying
system design. Each address location is associated with two
18-bit words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
256Kx18
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read
Ad
d. D
e
code
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
18
18
36
Write
18
BWS
0
Vref
W
ri
te A
dd.
Decode
Data Reg
Write
Data Reg
Memory
Array
256Kx18
Memory
Array
18
18
A
(17:0)
18
18
C
C
BWS
1
Logic Block Diagram (
CY7C1302DV25
)
"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.
Summary
CY7C1302DV25 Document #: 38-05625 Rev. *A Page 3 of 18 Introduction Functional Overview The CY7C1302DV25 is a synchronous pipelined Burst SRAMequipped with both a Read port and a Write port. The Readport is dedicated to Read operations and the Write port isdedicated to Write operations. Data flows i...
CY7C1302DV25 Document #: 38-05625 Rev. *A Page 4 of 18 Synchronous internal circuitry will automatically three-statethe outputs following the next rising edge of the positive outputclock (C). This will allow for a seamless transition betweendevices without the insertion of wait states in a depthexpa...
CY7C1302DV25 Document #: 38-05625 Rev. *A Page 6 of 18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliantwith IEEE Standard #1149.1-1900. The TAP operates usingJEDEC standard 2.5V I/O logic le...
