Cypress CY7C1292DV18 - Manuals

Cypress CY7C1292DV18 – Manual in PDF format online.

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Manual

Manual Cypress CY7C1292DV18

Summary

Page 2 - Array; DOFF

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 2 of 23 Logic Block Diagram (CY7C1292DV18) CLK A (17:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D e cod e Read Data Reg. RPS WPS Q [17:0] Control Logic Address Register Reg. Reg. Reg. 18 18 18 36 18 BWS [1:0] V REF W rite...

Page 3 - Pin Configurations

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 3 of 23 Pin Configurations CY7C1292DV18 (512K x 18) 2 3 4 5 6 7 1 AB CD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/144M NC/36M BWS 1 K WPS NC/288M Q9 D9 NC NC NC TDO NC NC D13 NC NC NC TCK NC D10 A NC K BWS 0 V SS A A A Q10 V SS V SS...

Page 4 - Pin Definitions

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 4 of 23 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations . CY7C1292DV18 - D [17:0] CY7C1294DV18 - D [35:0] WPS Input- Sync...

Page 5 - Functional Overview

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 5 of 23 Functional Overview The CY7C1292DV18 and CY7C1294DV18 are synchronouspipelined Burst SRAMs equipped with both a Read port and aWrite port. The Read port is dedicated to Read operations andthe Write port is dedicated to Write operati...

Page 6 - to allow the SRAM to adjust its

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 6 of 23 Byte Write Operations Byte Write operations are supported by the CY7C1292DV18.A Write operation is initiated as described in the Write Opera-tions section above. The bytes that are written are determinedby BWS 0 and BWS 1 , which ar...

Page 8 - Write Cycle Descriptions; BWS

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 8 of 23 Write Cycle Descriptions (CY7C1294DV18) [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L-H - During the Data portion of a Write sequence, all four bytes (D [35:0] ) are written into the device. L L L L - L-H During the Data por...

Page 9 - Instruction Register; ) when the BYPASS instruction is executed.

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 9 of 23 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliantwith IEEE Standard #1149.1-1900. The TAP operates usingJEDEC standard 1.8V...

Page 10 - and t

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 10 of 23 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded into the instruction register. It also places theinstruction register between the TDI and TDO pins and allowsthe IDCODE to be shifted out of the device...

Page 11 - TAP Controller State Diagram

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 11 of 23 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. TAP Controller State Diagram [9] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SELE...

Page 12 - TAP Controller Block Diagram; TAP Controller; TAP Electrical Characteristics; Parameter

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 12 of 23 TAP Controller Block Diagram 0 0 1 2 . . 29 30 31 Boundary Scan Register Identification Register 0 1 2 . . . . 106 0 1 2 Instruction Register Bypass Register SelectionCircuitry SelectionCircuitry TAP Controller TDI TDO TCK TMS TAP ...

Page 13 - TAP AC Switching Characteristics; TAP Timing and Test Conditions; Test Clock

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 13 of 23 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min. Max. Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Set-up Tim...

Page 15 - Boundary Scan Order; Bump ID; Internal

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 15 of 23 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 6...

Page 16 - DLL Constraints

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 16 of 23 Power-Up Sequence in QDR-II SRAM [16] QDR-II SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Power-Up Sequence • Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW) ...

Page 17 - Electrical Characteristics; Capacitance

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 17 of 23 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature withPower Applied ............................................. –55°C to +125°...

Page 18 - Thermal Resistance; AC Test Loads and Waveforms; ZQ

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 18 of 23 Note: 22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250 Ω , V DDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the sp...

Page 19 - Switching Characteristics

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 19 of 23 Switching Characteristics Over the Operating Range [22, 23] Cypress Parameter Consortium Parameter Description 250 MHz 200 MHz 167 MHz Unit Min. Max. Min. Max. Min. Max. t POWER t KHKH V DD (Typical) to the first Access [24] 1 1 1 ...

Page 20 - Switching Waveforms; RPS

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 20 of 23 Switching Waveforms [27, 28, 29] Read/Write/Deselect Sequence Notes: 27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.28. Output are disabled (High-Z) on...

Page 21 - Ordering Information

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 21 of 23 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code Package Diagram...

Page 22 - Package Diagram

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 22 of 23 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied ...

Page 23 - Document History Page; Issue Date

CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 23 of 23 Document History Page Document Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst ArchitectureDocument Number: 001-00350 REV. ECN No. Issue Date Orig. of Change Description of Change ** 380737 See ECN SYT New data s...