Cypress CY7C1292DV18 - Manual
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Table of Contents:
- Page 2 – Array; DOFF
- Page 3 – Pin Configurations
- Page 4 – Pin Definitions
- Page 5 – Functional Overview
- Page 6 – to allow the SRAM to adjust its
- Page 8 – Write Cycle Descriptions; BWS
- Page 9 – Instruction Register; ) when the BYPASS instruction is executed.
- Page 10 – and t
- Page 11 – TAP Controller State Diagram
- Page 12 – TAP Controller Block Diagram; TAP Controller; TAP Electrical Characteristics; Parameter
- Page 13 – TAP AC Switching Characteristics; TAP Timing and Test Conditions; Test Clock
- Page 15 – Boundary Scan Order; Bump ID; Internal
- Page 16 – DLL Constraints
- Page 17 – Electrical Characteristics; Capacitance
- Page 18 – Thermal Resistance; AC Test Loads and Waveforms; ZQ
- Page 19 – Switching Characteristics
- Page 20 – Switching Waveforms; RPS
- Page 21 – Ordering Information
- Page 22 – Package Diagram
- Page 23 – Document History Page; Issue Date
9-Mbit QDR- II™ SRAM 2-Word
Burst Architecture
CY7C1292DV18
CY7C1294DV18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-00350 Rev. *A
Revised July 20, 2006
Features
• Separate Independent Read and Write data ports
— Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x 18 and x 36 configurations
• Full data coherency, providing most current data
• Core V
DD
= 1.8V (±0.1V); I/O V
DDQ
= 1.4V to V
DD
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1292DV18 – 512K x 18
CY7C1294DV18 – 256K x 36
Functional Description
The CY7C1292DV18 and CY7C1294DV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR™-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write opera-
tions. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K clock.
Accesses to the QDR-II Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 18-bit words (CY7C1292DV18) or 36-bit
words (CY7C1294DV18) that burst sequentially into or out of
the device. Since data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and
C and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
600
550
500
mA
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Summary
CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 2 of 23 Logic Block Diagram (CY7C1292DV18) CLK A (17:0) Gen. K K Control Logic Address Register D [17:0] Read Add. D e cod e Read Data Reg. RPS WPS Q [17:0] Control Logic Address Register Reg. Reg. Reg. 18 18 18 36 18 BWS [1:0] V REF W rite...
CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 3 of 23 Pin Configurations CY7C1292DV18 (512K x 18) 2 3 4 5 6 7 1 AB CD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/144M NC/36M BWS 1 K WPS NC/288M Q9 D9 NC NC NC TDO NC NC D13 NC NC NC TCK NC D10 A NC K BWS 0 V SS A A A Q10 V SS V SS...
CY7C1292DV18CY7C1294DV18 Document #: 001-00350 Rev. *A Page 4 of 23 Pin Definitions Pin Name I/O Pin Description D [x:0] Input- Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations . CY7C1292DV18 - D [17:0] CY7C1294DV18 - D [35:0] WPS Input- Sync...
