Cypress CY7C1268V18 - Manuals

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Manual

Manual Cypress CY7C1268V18

Summary

Page 2 - rray; Array

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1266V18) Logic Block Diagram (CY7C1277V18) CLK A (20:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 8...

Page 4 - Pin Configurations

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 4 of 27 Pin Configurations CY7C1266V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K R/W NC/144M NC NC NC NC NC TDO NC NC N...

Page 6 - Pin Definitions; “Switching Character-

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input/Output-Synchronous Data Input/Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins...

Page 8 - Functional Overview; Write Operations; “Switching Characteristics” on page 22

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 8 of 27 Functional Overview The CY7C1266V18, CY7C1277V18, CY7C1268V18, andCY7C1270V18 are synchronous pipelined Burst SRAMsequipped with a DDR interface. Accesses for both ports are initiated on the Positive Inp...

Page 9 - DLL Considerations in; Application Example; Figure 1; Figure 1. Application Example; Truth Table; Operation; BUS; DQ

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 9 of 27 Delay Lock Loop (DLL) These chips use a DLL that is designed to function between 120MHz and the specified maximum clock frequency. The DLL maybe disabled by applying ground to the DOFF pin. When the DLLi...

Page 11 - Write Cycle Descriptions; BWS

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 11 of 27 Write Cycle Descriptions The write cycle description table for CY7C1270V18 follows. [2, 8] BWS 0 BWS 1 BWS 2 BWS 3 K K Comments L L L L L-H – During the data portion of a write sequence, all four bytes ...

Page 12 - Instruction Register; Boundary Scan Register

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 12 of 27 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test accessport (TAP) in the FBGA package. This part is fully compliant withIEEE Standard #1149.1-2001. The TAP ope...

Page 13 - and t; ). The SRAM clock input might not be captured

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 13 of 27 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code intothe instruction register. It also places the instruction registerbetween the TDI and TDO pins and shifts the IDCODE out of thedevic...

Page 14 - TAP Controller State Diagram; The state diagram for the TAP controller follows.

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 14 of 27 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] TEST-LOGICRESET TEST-LOGIC/IDLE SELECTDR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR SELECTIR-SCAN CA...

Page 15 - TAP Controller

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 15 of 27 TAP Controller Block Diagram TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min Max Unit V OH1 Output HIGH Voltage I OH = − 2.0 mA 1.4 V V OH2...

Page 16 - Figure 2

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 16 of 27 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK...

Page 18 - Boundary Scan Order; Bump ID; Internal

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 18 of 27 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 ...

Page 19 - Power Up Sequence; DLL Constraints; Power Up Waveforms; Figure 3. Power Up Waveforms; DOFF; Unstable Clock

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 19 of 27 Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must be powered up and initialized in apredefined manner to prevent undefined operations. Duringpower up, when the DOFF is tied HIGH, the DLL gets locked ...

Page 20 - Electrical Characteristics; DC Electrical Characteristics

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 20 of 27 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Tem...

Page 21 - Capacitance; Thermal Resistance

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 21 of 27 Capacitance [20] Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V V DDQ = 1.5V 5 pF C CLK Clock Input Capacitance 4 pF C O Output Capacitance 5 ...

Page 22 - Switching Characteristics

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 22 of 27 Switching Characteristics Over the Operating Range [21, 22] Cypress Parameter Consortium Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit Min Max Min Max Min Max Min Max t POWER V DD (Typical)...

Page 23 - Switching Waveforms; Figure 5. Waveform for 2.5 Cycle Read Latency; DON’T CARE; t CQD

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 23 of 27 Switching Waveforms Read/Write/Deselect Sequence [29, 30] Figure 5. Waveform for 2.5 Cycle Read Latency 1 2 3 4 5 6 7 8 9 10 READ READ NOP WRITE WRITE t NOP 11 LD R/W A tKH tKL tCYC tHC tSA tHA DON’T CA...

Page 24 - Ordering Information; for actual products offered.

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 24 of 27 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) ...

Page 26 - Package Diagram

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 26 of 27 Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 ! 0).#/2.%2 ¼ ¼ 8 -#!" -# " ! 8 ¼ -!8 3%!4).'0,!.% ¼ # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - ....

Page 27 - Document History Page; Issue Date

Document Number: 001-06347 Rev. *D Revised March 11, 2008 Page 27 of 27 All product and company names mentioned in this document are the trademarks of their respective holders. CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 © Cypress Semiconductor Corporation, 2006-2008. The information contained ...