Cypress CY7C1268V18 - Manual
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Table of Contents:
- Page 2 – rray; Array
- Page 4 – Pin Configurations
- Page 6 – Pin Definitions; “Switching Character-
- Page 8 – Functional Overview; Write Operations; “Switching Characteristics” on page 22
- Page 9 – DLL Considerations in; Application Example; Figure 1; Figure 1. Application Example; Truth Table; Operation; BUS; DQ
- Page 11 – Write Cycle Descriptions; BWS
- Page 12 – Instruction Register; Boundary Scan Register
- Page 13 – and t; ). The SRAM clock input might not be captured
- Page 14 – TAP Controller State Diagram; The state diagram for the TAP controller follows.
- Page 15 – TAP Controller
- Page 16 – Figure 2
- Page 18 – Boundary Scan Order; Bump ID; Internal
- Page 19 – Power Up Sequence; DLL Constraints; Power Up Waveforms; Figure 3. Power Up Waveforms; DOFF; Unstable Clock
- Page 20 – Electrical Characteristics; DC Electrical Characteristics
- Page 21 – Capacitance; Thermal Resistance
- Page 22 – Switching Characteristics
- Page 23 – Switching Waveforms; Figure 5. Waveform for 2.5 Cycle Read Latency; DON’T CARE; t CQD
- Page 24 – Ordering Information; for actual products offered.
- Page 26 – Package Diagram
- Page 27 – Document History Page; Issue Date
CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18
36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.5 Cycle Read Latency)
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 001-06347 Rev. *D
Revised March 11, 2008
Features
■
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
■
300 MHz to 400 MHz clock for high bandwidth
■
2-Word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 800 MHz) at 400 MHz
■
Read latency of 2.5 clock cycles
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Core V
DD
= 1.8V ± 0.1V; IO V
DDQ
= 1.4V to V
DD
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both in Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1266V18 – 4M x 8
CY7C1277V18 – 4M x 9
CY7C1268V18 – 2M x 18
CY7C1270V18 – 1M x 36
Functional Description
The CY7C1266V18, CY7C1277V18, CY7C1268V18, and
CY7C1270V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1266V18), 9-bit words (CY7C1277V18),
18-bit words (CY7C1268V18), or 36-bit words (CY7C1270V18),
that burst sequentially into or out of the device.
Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, sharing the same physical
pins as the data inputs, D) are tightly matched to the two output
echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
400 MHz
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
400
375
333
300
MHz
Maximum Operating Current
1280
1210
1080
1000
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V
DDQ
= 1.4V to V
DD
.
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Summary
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1266V18) Logic Block Diagram (CY7C1277V18) CLK A (20:0) Gen. K K Control Logic Address Register R ead Add. Decode Read Data Reg. R/W DQ [7:0] Output Logic Reg. Reg. Reg. 8 8 16 8...
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 4 of 27 Pin Configurations CY7C1266V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 2 3 4 5 6 7 1 A B CD E F G H J K L M N P R A CQ NC NC NC NC DOFF NC NC/72M A NWS 1 K R/W NC/144M NC NC NC NC NC TDO NC NC N...
CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18 Document Number: 001-06347 Rev. *D Page 6 of 27 Pin Definitions Pin Name IO Pin Description DQ [x:0] Input/Output-Synchronous Data Input/Output Signals . Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins...
