Cypress CY7C1217H - Manuals

Page 2 - Logic Block Diagram; ZZ; SLEEP

CY7C1217H Document #: 38-05670 Rev. *B Page 2 of 16 Logic Block Diagram ADDRESSREGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQs DQP A DQP B DQP C DQP D A0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3...

Page 3 - Pin Configuration

CY7C1217H Document #: 38-05670 Rev. *B Page 3 of 16 Pin Configuration 100-Pin TQFP A A A A A 1 A 0 NC/7 2 M NC/3 6 M V SS V DD NC /9 M A A A A A NC /4M DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A ...

Page 4 - Pin Descriptions

CY7C1217H Document #: 38-05670 Rev. *B Page 4 of 16 Pin Descriptions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 32K address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled active. ...

Page 5 - Functional Overview

CY7C1217H Document #: 38-05670 Rev. *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlledby the rising edge of the clock. Maximum access delay fromthe clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1217H supports secondary cache in systemsutilizi...

Page 7 - Truth Table for Read/Write; Read

CY7C1217H Document #: 38-05670 Rev. *B Page 7 of 16 Truth Table for Read/Write [2, 3] Function GW BWE BW D BW C BW B BW A Read H H X X X X Read H L H H H H Write Byte (A, DQP A ) H L H H H L Write Byte (B, DQP B ) H L H H L H Write Bytes (B, A, DQP A , DQP B ) H L H H L L Write Byte (C, DQP C ) H L ...

Page 8 - Electrical Characteristics

CY7C1217H Document #: 38-05670 Rev. *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide-lines, not tested.) Storage Temperature ................................ –65 ° C to + 150 ° C Ambient Temperature withPower Applied ..........................................

Page 9 - Capacitance; Thermal Resistance; AC Test Loads and Waveforms

CY7C1217H Document #: 38-05670 Rev. *B Page 9 of 16 Capacitance [9] Parameter Description Test Conditions 100 TQFP Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V. V DDQ = 2.5V 5 pF C CLK Clock Input Capacitance 5 pF C I/O Input/Output Capacitance 5 pF Thermal Resistance [9] Pa...

Page 10 - Switching Characteristics

CY7C1217H Document #: 38-05670 Rev. *B Page 10 of 16 Switching Characteristics Over the Operating Range [10, 11] Parameter Description 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (Typical) to the First Access [12] 1 1 ms Clock t CYC Clock Cycle Time 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t C...

Page 11 - Timing Diagrams; Read Cycle Timing

CY7C1217H Document #: 38-05670 Rev. *B Page 11 of 16 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is LOW, CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 t CEH tCES D...

Page 12 - Write Cycle Timing

CY7C1217H Document #: 38-05670 Rev. *B Page 12 of 16 Write Cycle Timing [16, 17] Note: 17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Timing Diagrams (continued) tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High-Z BURST READ BURST WRITE ...

Page 14 - ZZ Mode Timing; CLK

CY7C1217H Document #: 38-05670 Rev. *B Page 14 of 16 ZZ Mode Timing [20, 21] Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.21. DQs are in High-Z when exiting ZZ sleep mode. Timing Diagrams (continued...

Page 15 - Ordering Information; Commercial; Package Diagram

CY7C1217H Document #: 38-05670 Rev. *B Page 15 of 16 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress pro...

Page 16 - Document History Page; Issue Date

CY7C1217H Document #: 38-05670 Rev. *B Page 16 of 16 Document History Page Document Title: CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAMDocument Number: 38-05670 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 345879 See ECN PCI New Data Sheet *A 430677 See ECN NXR Changed addr...