Cypress CY7C1217H - Manual
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Table of Contents:
- Page 2 – Logic Block Diagram; ZZ; SLEEP
- Page 3 – Pin Configuration
- Page 4 – Pin Descriptions
- Page 5 – Functional Overview
- Page 7 – Truth Table for Read/Write; Read
- Page 8 – Electrical Characteristics
- Page 9 – Capacitance; Thermal Resistance; AC Test Loads and Waveforms
- Page 10 – Switching Characteristics
- Page 11 – Timing Diagrams; Read Cycle Timing
- Page 12 – Write Cycle Timing
- Page 14 – ZZ Mode Timing; CLK
- Page 15 – Ordering Information; Commercial; Package Diagram
- Page 16 – Document History Page; Issue Date
CY7C1217H
1-Mbit (32K x 36) Flow-Through Sync SRAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05670 Rev. *B
Revised July 6, 2006
Features
• 32K x 36 common I/O
• 3.3V core power supply (V
DD
)
• 2.5V/3.3V I/O power supply (V
DDQ
)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1217H is a 32K x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1217H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1217H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.0
ns
Maximum Operating Current
225
205
mA
Maximum Standby Current
40
40
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
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Summary
CY7C1217H Document #: 38-05670 Rev. *B Page 2 of 16 Logic Block Diagram ADDRESSREGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQs DQP A DQP B DQP C DQP D A0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3...
CY7C1217H Document #: 38-05670 Rev. *B Page 3 of 16 Pin Configuration 100-Pin TQFP A A A A A 1 A 0 NC/7 2 M NC/3 6 M V SS V DD NC /9 M A A A A A NC /4M DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A ...
CY7C1217H Document #: 38-05670 Rev. *B Page 4 of 16 Pin Descriptions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 32K address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 are sampled active. ...
