Cypress CY7B9920 - Manuals

CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 5 of 11 AC Test Loads and Waveforms Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V CC = 5.0...

CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 8 of 11 AC Timing Diagrams Figure 1. AC Timing Diagrams Figure 2. Zero Skew and Zero Delay Clock Driver t ODCV t ODCV t REF REF FB Q OTHER Q t RPWH t RPWL t PD t SKEW t SKEW t JR SYSTEM CLOCK FBREFFS Q0Q1 Q2Q3Q4Q5 Q6Q7 TEST Z 0 LOAD LOAD LOAD L...

CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 9 of 11 Operational Mode Descriptions Figure 2 shows the device configured as a zero skew clock buffer. In this mode the 7B9910/9920 is used as the basis for alow skew clock distribution tree. The outputs are aligned and mayeach drive a termina...

CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 10 of 11 Ordering Information Accuracy (ps) Ordering Code Package Type Operating Range 250 CY7B9910–2SC 24-Pb Small Outline IC Commercial CY7B9910–2SCT 24-Pb Small Outline IC - Tape and Reel Commercial CY7B9920–2SC [20] 24-Pb Small Outline IC C...

Document Number: 38-07135 Rev. *B Revised August 07, 2007 Page 11 of 11 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registeredtrademarks referenced herein are property of the...