Cypress CY7B9920 - Manual
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Table of Contents:
- Page 2 – Block Diagram Description; Pin Definitions; Signal Name; TEST MODE; SOIC
- Page 3 – Range; Commercial
- Page 4 – Electrical Characteristics
- Page 5 – Switching Characteristics
- Page 8 – AC Timing Diagrams; Figure 1. AC Timing Diagrams
- Page 9 – Operational Mode Descriptions; Figure 2
- Page 10 – Ordering Information; Accuracy; Package Diagram
- Page 11 – Document History; Issue Date
CY7B9910
CY7B9920
Low Skew Clock Buffer
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document Number: 38-07135 Rev. *B
Revised August 07, 2007
Features
■
All outputs skew <100 ps typical (250 max.)
■
15 to 80 MHz output operation
■
Zero input to output delay
■
50% duty cycle outputs
■
Outputs drive 50
Ω
terminated lines
■
Low operating current
■
24-pin SOIC package
■
Jitter:<200 ps peak to peak, <25 ps RMS
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50
Ω
. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL enables “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
TEST
FB
REF
VOLTAGE
CONTROLLED
OSCILLATOR
FS
Q0
FILTER
PHASE
FREQ
DET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Logic Block Diagram
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Summary
CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 2 of 11 Pin Configuration Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 andCY7B9920 to operate as described in Block Diagram Description . For testing purpose...
CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 3 of 11 Maximum Ratings Operating outside these boundaries may affect the performanceand life of the device. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Ambient Temperature wit...
CY7B9910CY7B9920 Document Number: 38-07135 Rev. *B Page 4 of 11 Electrical Characteristics Over the Operating Range CY7B9910 CY7B9920 Parameter Description Test Conditions Min Max Min Max Unit V OH Output HIGH Voltage V CC = Min, I OH = –16 mA 2.4 V V CC = Min, I OH =–40 mA V CC – 0.75 V OL Output L...
