Cypress CY62157EV18 - Manuals

Page 2 - W DE; Note; Top View

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 2 of 12 Logic Block Diagram Pin Configuration [3] 512K x 16 RAM Array IO 0 –IO 7 RO W DE CO DE R A 8 A 7 A 6 A 5 A 2 COLUMN DECODER A 11 A 12 A 13 A 14 A 15 SE NS E AMP S DATA IN DRIVERS OE A 4 A 3 IO 8 –IO 15 WE BLE BHE A 16 A 0 A 1 A 17 A 9 BHEB...

Page 3 - Electrical Characteristics; Notes; Full Device AC operation assumes a 100; s wait time after V; spec. Other inputs can be left floating.

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 3 of 12 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................ –65°C to + 150°CAmbient Temperature withPower Applied ..............

Page 4 - DATA RETENTION MODE; CE; Full device operation requires linear V; ramp from V; to V

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 4 of 12 Thermal Resistance [8] Parameter Description Test Conditions BGA Unit Θ JA Thermal Resistance (Junction to Ambient) Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 72 ° C/W Θ JC Thermal Resistance (Junction to Case) ...

Page 5 - Switching Characteristics; “AC Test Loads and Waveforms” on page 4

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 5 of 12 Switching Characteristics (Over the Operating Range) [11, 12] Parameter Description 55 ns Unit Min Max Read Cycle t RC Read Cycle Time 55 ns t AA Address to Data Valid 55 ns t OHA Data Hold from Address Change 10 ns t ACE CE 1 LOW and CE 2...

Page 6 - Switching Waveforms; Read Cycle 1

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 6 of 12 Switching Waveforms Read Cycle 1 (Address Transition Controlled) [17, 18] Read Cycle 2 (OE Controlled) [18, 19] PREVIOUS DATA VALID DATA VALID RC t AA t OHA t RC ADDRESS DATA OUT 50% 50% DATA VALID t RC t ACE t DOE t LZOE t LZCE t PU HIGH ...

Page 7 - or CE; goes HIGH and CE; , the output remains in a high impedance state.

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 7 of 12 Write Cycle 1 (WE Controlled) [16, 20, 21] Write Cycle 2 (CE 1 or CE 2 Controlled) [16, 20, 21] Switching Waveforms (continued) t HD t SD t PWE t SA t HA t AW t SCE t WC t HZOE VALID DATA t BW NOTE 22 CE 1 ADDRESS CE 2 WE DATA IO OE BHE/BL...

Page 8 - HZWE

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 8 of 12 Write Cycle 3 (WE Controlled, OE LOW) [21] Write Cycle 4 (BHE/BLE Controlled, OE LOW) [21] Switching Waveforms (continued) VALID DATA t HD t SD t LZWE t PWE t SA t HA t AW t SCE t WC t HZWE t BW NOTE 22 CE 1 ADDRESS CE 2 WE DATA IO BHE/BLE...

Page 10 - Package Diagrams

Document #: 38-05490 Rev. *D Page 10 of 12 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for theuse of any circuitry other than circuitry embodied in a Cypress product....

Page 11 - Document History; Change

CY62157EV18 MoBL ® Document #: 38-05490 Rev. *D Page 11 of 12 Document History Document Title: CY62157EV18 MoBL ® 8-Mbit (512K x 16) Static RAM Document Number:38-05490 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 202862 See ECN AJU New Data Sheet *A 291272 See ECN SYT Converted ...