Page 2 - ROW DECODER; OE; Top View
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 2 of 12 Logic Block Diagram Pin Configurations [3, 4] 256K x 16 RAM Array IO 0 –IO 7 ROW DECODER A 8 A 7 A 6 A 5 A 2 COLUMN DECODER A 11 A 12 A 13 A 14 A 15 SENSE AMPS DATA IN DRIVERS OE A 4 A 3 IO 8 –IO 15 CE WE BHE A 16 A 0 A 1 A 9 A 10 BLE A 17...
Page 3 - Electrical Characteristics; Full device AC operation assumes a minimum of 100
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 3 of 12 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.Storage Temperature ................................ –65°C to + 150°CAmbient Temperature with Power Applied .........
Page 4 - DATA RETENTION MODE; CE; Full device operation requires linear V; ramp from V; to V
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 4 of 12 Capacitance (For All Packages) [9] Parameter Description Test Conditions Max Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = V CC(typ) 10 pF C OUT Output Capacitance 10 pF Thermal Resistance [9] Parameter Description Test Conditi...
Page 5 - Switching Characteristics; “AC Test Loads and Waveforms” on page 4
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 5 of 12 Switching Characteristics (Over the Operating Range) [11, 12] Parameter Description 45 ns Unit Min Max Read Cycle t RC Read Cycle Time 45 ns t AA Address to Data Valid 45 ns t OHA Data Hold from Address Change 10 ns t ACE CE LOW to Data Va...
Page 6 - Switching Waveforms; Read Cycle 1; PREVIOUS DATA VALID; RC; ADDRESS
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 6 of 12 Switching Waveforms Read Cycle 1 (Address Transition Controlled) [16, 17] Read Cycle No. 2 (OE Controlled) [17, 18] PREVIOUS DATA VALID DATA VALID t RC t AA t OHA ADDRESS DATA OUT 50% 50% DATA VALID t RC t ACE t LZBE t LZCE t PU HIGH IMPED...
Page 7 - SA; If CE goes HIGH simultaneously with WE = V; , the output remains in a high impedance state.
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 7 of 12 Write Cycle No. 1 (WE Controlled) [15, 19, 20] Write Cycle No. 2 (CE Controlled) [15, 19, 20] Switching Waveforms (continued) t HD t SD t PWE t SA t HA t AW t WC t HZOE DATA IN NOTE 21 t BW t SCE DATA IO ADDRESS CE WE OE BHE/BLE t HD t SD ...
Page 10 - Package Diagrams
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 10 of 12 Package Diagrams Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150 A 1 A1 CORNER 0.75 0.75 Ø0.30±0.05(48X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.21±0.05 1.00 MAX C SEATING PLANE 0.55 MAX. 0.25 C 0.10 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4...
Page 12 - Document History Page; Change
CY62146EV30 MoBL ® Document #: 38-05567 Rev. *C Page 12 of 12 Document History Page Document Title:CY62146EV30 MoBL ® , 4-Mbit (256K x 16) Static RAM Document Number: 38-05567 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 223225 See ECN AJU New Data Sheet *A 247373 See ECN SYT Cha...