Cypress CY14B108M - Manuals

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Manual

Manual Cypress CY14B108M

Summary

Page 2 - PRELIMINARY; Pinouts; DQ

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 2 of 29 Pinouts Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A 0 – A 19 Input Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration . A...

Page 3 - Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 2

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 3 of 29 Device Operation The CY14B108K/CY14B108M nvSRAM is made up of twofunctional components paired in the same physical cell. Theseare a SRAM memory cell and a nonvolatile QuantumTrap cell.The SRAM memory cell operates as a stand...

Page 4 - Software STORE

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 4 of 29 power-on-recall, the MPU must be active or the WE held inactiveuntil the MPU comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore, andHardware STORE operations are ignored unless at least onewrite operatio...

Page 5 - Preventing AutoStore; Table 2. Mode Selection

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 5 of 29 Preventing AutoStore The AutoStore function is disabled by initiating an AutoStoredisable sequence. A sequence of read operations is performedin a manner similar to the Software STORE initiation. To initiatethe AutoStore dis...

Page 6 - Data Protection; Noise Considerations

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 6 of 29 Data Protection The CY14B108K/CY14B108M protects data from corruptionduring low voltage conditions by inhibiting all externally initiatedSTORE and write operations. The low voltage condition isdetected when V CC is less than...

Page 7 - Real Time Clock Operation; Table 4; Setting the Clock; Table 3. RTC Backup Time

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 7 of 29 Real Time Clock Operation nvTime Operation The CY14B108K/CY14B108M offers internal registers thatcontain clock, alarm, watchdog, interrupt, and control functions.RTC registers use the last 16 address locations of the SRAM.In...

Page 8 - Calibrating the Clock; Alarm; Watchdog Timer; Figure 3

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 8 of 29 calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ condition. The value of OSCF must be reset to ‘0’ when the time registersare written for the first time. This initializes the state of this ...

Page 9 - Figure 3. Watchdog Timer Block Diagram; Power Monitor; AutoStore Operation; Interrupts; Interrupt Register; Stopping and Starting the Oscillator

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 9 of 29 Figure 3. Watchdog Timer Block Diagram . Power Monitor The CY14B108K provides a power management scheme withpower fail interrupt capability. It also controls the internal switchto backup power for the clock and protects the ...

Page 10 - Figure 4. RTC Recommended Component Configuration; Xout; WDF - Watchdog Timer Flag

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 10 of 29 Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Recommended Values Y 1 = 32.768 KHz (6 pF) C 1 = 21 pF C 2 = 21 pF Note: The recommended values for C1 and C2 include board trace capacitan...

Page 11 - Table 4. RTC Register Map

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 11 of 29 Table 4. RTC Register Map [7] Register BCD Format Data [8] Function/Range CY14B108K CY14B108M D7 D6 D5 D4 D3 D2 D1 D0 0xFFFFF 0x7FFFF 10s Years Years Years: 00–99 0xFFFFE 0x7FFFE 0 0 0 10s Months Months Months: 01–12 0xFFFF...

Page 13 - Register; Interrupt Status/Control

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 13 of 29 Register Description CY14B108K CY14B108M 0xFFFF8 0x7FFF8 Calibration/Control D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibration Sign Calibration OSCEN Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the...

Page 14 - Table 5. Register Map Detail

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 14 of 29 Register Description CY14B108K CY14B108M 0xFFFF4 0x7FFF4 Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M M...

Page 15 - Maximum Ratings; DC Electrical Characteristics

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 15 of 29 Maximum Ratings Exceeding maximum ratings may impair the useful life of thedevice. These user guidelines are not tested. Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulated Storage ...

Page 16 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 16 of 29 AC Test Conditions Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <3 ns Input and Output Timing Reference Levels .............

Page 18 - AC Switching Characteristics

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 18 of 29 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [15] t RC Read Cycle ...

Page 19 - Switching Waveforms; Figure 8. SRAM Read Cycle 2: CE Controlled

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 19 of 29 Switching Waveforms Figure 8. SRAM Read Cycle 2: CE Controlled [3, 15, 19] Figure 9. SRAM Write Cycle 1: WE Controlled [3, 18, 19, 20] Address Valid Address Data Output Output Data Valid Standby Active High Impedance CE OE ...

Page 20 - Figure 10. SRAM Write Cycle 2: CE Controlled

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 20 of 29 Switching Waveforms Figure 10. SRAM Write Cycle 2: CE Controlled [3, 18, 19, 20] Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled [5, 18, 19, 20, 21] Data Output Data Input Input Data Valid High Impedance Address Valid...

Page 21 - AutoStore/Power Up RECALL; RWI

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 21 of 29 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [22] Power Up RECALL Duration 20 20 20 ms t STORE [23] STORE Cycle Duration 8 8 8 ms t DELAY [24] Time Allowed to Com...

Page 22 - Software Controlled STORE and RECALL Cycle

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 22 of 29 Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [27, 28] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC ST...

Page 23 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write latch set

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 23 of 29 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB To Output Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Width 15 15 15 ns Switching Wavefo...

Page 24 - For x8 Configuration

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 24 of 29 Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Inputs and Outputs [2] Mode Power H X X High Z Deselect/Power Down Standby L H L Data Out (DQ 0 –DQ 7 ); Read Active ...

Page 25 - Part Numbering Nomenclature; Cypress

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 25 of 29 Part Numbering Nomenclature Option:T - Tape & ReelBlank - Std. Speed: 20 - 20 ns25 - 25 ns Data Bus:K - x8 + RTCM - x16 + RTC Density: 108 - 8 Mb Voltage:B - 3.0V Cypress CY14 B 108 K ZS P 20 X C T NVSRAM 14 - AutoStore...

Page 26 - Ordering Information

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 26 of 29 Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 20 CY14B108K-ZS20XCT 51-85087 44-pin TSOPII Commercial CY14B108K-ZS20XC 51-85087 44-pin TSOPII CY14B108K-ZS20XIT 51-85087 44-pin TSO...

Page 27 - Package Diagrams

PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 27 of 29 Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) MAXMIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016)0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 ...

Page 29 - Document History Page; Worldwide Sales and Design Support; Change

Document #: 001-47378 Rev. ** Revised April 01, 2009 Page 29 of 29 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respectiveholders. PRELIMINARY CY14B108K, CY14B108M © Cyp...