Cypress CY14B108M - Manual
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Table of Contents:
- Page 2 – PRELIMINARY; Pinouts; DQ
- Page 3 – Device Operation; Truth Table For SRAM Operations; SRAM Read; Figure 2
- Page 4 – Software STORE
- Page 5 – Preventing AutoStore; Table 2. Mode Selection
- Page 6 – Data Protection; Noise Considerations
- Page 7 – Real Time Clock Operation; Table 4; Setting the Clock; Table 3. RTC Backup Time
- Page 8 – Calibrating the Clock; Alarm; Watchdog Timer; Figure 3
- Page 9 – Figure 3. Watchdog Timer Block Diagram; Power Monitor; AutoStore Operation; Interrupts; Interrupt Register; Stopping and Starting the Oscillator
- Page 10 – Figure 4. RTC Recommended Component Configuration; Xout; WDF - Watchdog Timer Flag
- Page 11 – Table 4. RTC Register Map
- Page 13 – Register; Interrupt Status/Control
- Page 14 – Table 5. Register Map Detail
- Page 15 – Maximum Ratings; DC Electrical Characteristics
- Page 16 – AC Test Conditions; Thermal Resistance; OUTPUT
- Page 18 – AC Switching Characteristics
- Page 19 – Switching Waveforms; Figure 8. SRAM Read Cycle 2: CE Controlled
- Page 20 – Figure 10. SRAM Write Cycle 2: CE Controlled
- Page 21 – AutoStore/Power Up RECALL; RWI
- Page 22 – Software Controlled STORE and RECALL Cycle
- Page 23 – Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write latch set
- Page 24 – For x8 Configuration
- Page 25 – Part Numbering Nomenclature; Cypress
- Page 26 – Ordering Information
- Page 27 – Package Diagrams
- Page 29 – Document History Page; Worldwide Sales and Design Support; Change
PRELIMINARY
CY14B108K, CY14B108M
8 Mbit (1024K x 8/512K x 16) nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 001-47378 Rev. **
Revised April 01, 2009
Features
■
20 ns, 25 ns, and 45 ns access times
■
Internally organized as 1024K x 8 (CY14B108K) or 512K x 16
(CY14B108M)
■
Hands off automatic STORE
on power down with only a small
capacitor
■
STORE
to QuantumTrap
®
nonvolatile elements is initiated by
software, device pin, or AutoStore
®
on power down
■
RECALL
to SRAM initiated by software or power up
■
High reliability
■
Infinite Read, Write, and RECALL cycles
■
200,000 STORE
cycles to QuantumTrap
■
20 year data retention
■
Single 3V +20%, –10% operation
■
Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock (RTC)
■
Watchdog timer
■
Clock alarm with programmable interrupts
■
Capacitor or battery backup for RTC
■
Commercial and industrial temperatures
■
44 and 54-pin TSOP II package
■
Pb-free and RoHS compliance
Functional Description
The Cypress CY14B108K/CY14B108M combines a 8-Mbit
nonvolatile static RAM with a full featured RTC in a monolithic
integrated circuit. The embedded nonvolatile elements incor-
porate QuantumTrap technology producing the world’s most
reliable nonvolatile memory. The SRAM is read and written
infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
STATIC RAM
ARRAY
2048 X 2048 X 2
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum
Trap
2048 X 2048 X 2
STORE
RECALL
V
CC
V
CAP
HSB
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
SOFTWARE
DETECT
A
14
- A
2
OE
CE
WE
BHE
BLE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
RTC
MUX
A
19
- A
0
X
out
X
in
INT
V
RTCbat
V
RTCcap
A
19
Logic Block Diagram
Notes
1. Address A
0
- A
19
for x8 configuration and Address A
0
- A
18
for x16 configuration.
2. Data DQ
0
- DQ
7
for x8 configuration and Data DQ
0
- DQ
15
for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
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Summary
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 2 of 29 Pinouts Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A 0 – A 19 Input Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration . A...
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 3 of 29 Device Operation The CY14B108K/CY14B108M nvSRAM is made up of twofunctional components paired in the same physical cell. Theseare a SRAM memory cell and a nonvolatile QuantumTrap cell.The SRAM memory cell operates as a stand...
PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev. ** Page 4 of 29 power-on-recall, the MPU must be active or the WE held inactiveuntil the MPU comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore, andHardware STORE operations are ignored unless at least onewrite operatio...
