Cypress CY14B101Q2 - Manuals

Cypress CY14B101Q2 – Manual in PDF format online.

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Manual

Manual Cypress CY14B101Q2

Summary

Page 2 - PRELIMINARY; Pinouts; GND; GND

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 2 of 22 Pinouts Figure 1. Pin Diagram - 8-Pin DFN [1, 2, 3] Figure 2. Pin Diagram - 16-Pin SOIC Table 1. Pin Definitions Pin Name I/O Type Description CS Input Chip Select . Activates the device when pulled LOW. Driving th...

Page 3 - Device Operation; Table 2; SRAM Write; Table 2. Feature Summary; Feature

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 3 of 22 Device Operation CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capabili...

Page 4 - Figure 3; Software Store Operation; Note; RECALL Operation

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 4 of 22 capacitor (V CAP ) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from V CC to charge the capacitor connected to th...

Page 5 - Serial Peripheral Interface; SPI Overview; Table 3

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 5 of 22 Note CY14B101Q2/CY14B101Q3 has AutoStore Enabled from the factory. In CY14B101Q1, V CAP pin is not present and AutoStore option is not available. The Autostore Enable and Disable instructions to CY14B101Q1 are igno...

Page 6 - SPI Modes; Figure 5; Figure 4. System Configuration Using SPI nvSRAM; Figure 5. SPI Mode 0; LSB; Figure 6. SPI Mode 3; SCK

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 6 of 22 SPI Modes CY14B101Q1/CY14B101Q2/CY14B101Q3 may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ■ SPI Mode 0 (CPOL=0, CPHA=0) ■ SPI Mode 3 (CPOL=1, CPHA=1) For bo...

Page 7 - SPI Operating Features; Power Up; DC Electrical Characteristics; SPI Functional Description

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 7 of 22 SPI Operating Features Power Up Power up is defined as the condition when the power supply is turned on and V CC crosses Vswitch voltage. During this time, the Chip Select (CS) must be allowed to follow the V CC vo...

Page 8 - Status Register

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 8 of 22 Status Register The status register bits are listed in Table 3 . The status register consists of Ready bit (RDY) and data protection bits BP1, BP0, WEN, and WPEN. The RDY bit can be polled to check the Ready or Bus...

Page 9 - Write Protection and Block Protection; Block Protection; Table 6

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 9 of 22 Write Protection and Block Protection CY14B101Q1/CY14B101Q2/CY14B101Q3 provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block ...

Page 10 - Table 7; Memory Access

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 10 of 22 Write Protect (WP) Pin The write protect pin (WP) is used to provide hardware write protection. WP pin enables all normal read and write operations when held HIGH. When the WP pin is brought LOW and WPEN bit is “1...

Page 11 - nvSRAM Special Instructions; Table 8; Software STORE

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 11 of 22 nvSRAM Special Instructions CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four special instructions which enables access to four nvSRAM specific functions: STORE, RECALL, ASDISB, and ASENB. Table 8 lists these instruc...

Page 12 - Software RECALL; HOLD Pin Operation

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 12 of 22 bit is cleared on the positive edge of CS following the STORE instruction. Software RECALL When a RECALL instruction is executed, nvSRAM performs a Software RECALL operation. To issue this instruction, the device ...

Page 13 - Maximum Ratings

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 13 of 22 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested.Storage Temperature ................................. –65 ° C to +150 ° C Maximum Accumulat...

Page 14 - AC Test Conditions; Thermal Resistance; OUTPUT

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 14 of 22 AC Test Conditions Input Pulse Levels.................................................... 0V to 3VInput Rise and Fall Times (10% - 90%) ....................... <3 nsInput and Output Timing Reference Levels........

Page 15 - AC Switching Characteristics

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 15 of 22 AC Switching Characteristics Cypress Parameter Alt. Parameter Description 40MHz Unit Min Max f SCK f SCK Clock Frequency, SCK 40 MHz t CL t WL Clock Pulse Width Low 11 ns t CH t WH Clock Pulse Width High 11 ns t C...

Page 16 - AutoStore or Power Up RECALL

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 16 of 22 AutoStore or Power Up RECALL Parameters Description CY‘4B101QxA Unit Min Max t FA [7] Power Up RECALL Duration 20 ms t STORE [8] STORE Cycle Duration 8 ms t DELAY [9] Time Allowed to Complete SRAM Cycle 25 ns V SW...

Page 17 - Software Controlled STORE and RECALL Cycles; RECALL Duration; Soft Sequence Processing Time; Switching Waveforms

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 17 of 22 Software Controlled STORE and RECALL Cycles Parameter Description CY14B101Q1 Unit Min Max t RECALL RECALL Duration 200 μ s t SS [12, 13] Soft Sequence Processing Time 100 μ s Switching Waveforms Figure 24. Softwar...

Page 18 - Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write Latch not set

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 18 of 22 Hardware STORE Cycle Parameter Description CY14B101Q1 Unit Min Max t DHSB HSB To Output Active Time when write latch not set 25 ns t PHSB Hardware STORE Pulse Width 15 ns Switching Waveforms Figure 26. Hardware ST...

Page 19 - Ordering Information; Part Numbering Nomenclature

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 19 of 22 Ordering Information Ordering Code Package Diagram Package Type Operating Range CY14B101Q1-LHXIT 001-50671 8 DFN (with WP) Industrial CY14B101Q1-LHXI 001-50671 8 DFN (with WP) CY14B101Q1-LHXCT 001-50671 8 DFN (wit...

Page 20 - Package Diagrams

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 20 of 22 Package Diagrams Figure 27. 8-Pin (300 mil) DFN Package (001-50671) 1. ALL DIMENSIONS ARE IN MILLIMETERS 3. BASED ON REF JEDEC # MO-240 EXCEPT DIMENSIONS (L) and (b) NOTES: 2. PACKAGE WEIGHT: TBD 001-50671 *A [+] ...

Page 22 - Document History Page; Worldwide Sales and Design Support; Change

Document #: 001-50091 Rev. *A Revised February 2, 2009 Page 22 of 22 AutoStore and QuantumTrap are trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document are the trademarks of their respective holders. PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 © Cypress ...