Cypress CY14B101Q2 - Manual

Cypress CY14B101Q2

Cypress CY14B101Q2 – Manual, read for free online in PDF format. We hope this helps you resolve any issues you may have. If you have further questions, please contact us through the contact form.

1 Page 1
2 Page 2
3 Page 3
4 Page 4
5 Page 5
6 Page 6
7 Page 7
8 Page 8
9 Page 9
10 Page 10
11 Page 11
12 Page 12
13 Page 13
14 Page 14
15 Page 15
16 Page 16
17 Page 17
18 Page 18
19 Page 19
20 Page 20
21 Page 21
22 Page 22
Page: / 22

Table of Contents:

  • Page 2 – PRELIMINARY; Pinouts; GND; GND
  • Page 3 – Device Operation; Table 2; SRAM Write; Table 2. Feature Summary; Feature
  • Page 4 – Figure 3; Software Store Operation; Note; RECALL Operation
  • Page 5 – Serial Peripheral Interface; SPI Overview; Table 3
  • Page 6 – SPI Modes; Figure 5; Figure 4. System Configuration Using SPI nvSRAM; Figure 5. SPI Mode 0; LSB; Figure 6. SPI Mode 3; SCK
  • Page 7 – SPI Operating Features; Power Up; DC Electrical Characteristics; SPI Functional Description
  • Page 8 – Status Register
  • Page 9 – Write Protection and Block Protection; Block Protection; Table 6
  • Page 10 – Table 7; Memory Access
  • Page 11 – nvSRAM Special Instructions; Table 8; Software STORE
  • Page 12 – Software RECALL; HOLD Pin Operation
  • Page 13 – Maximum Ratings
  • Page 14 – AC Test Conditions; Thermal Resistance; OUTPUT
  • Page 15 – AC Switching Characteristics
  • Page 16 – AutoStore or Power Up RECALL
  • Page 17 – Software Controlled STORE and RECALL Cycles; RECALL Duration; Soft Sequence Processing Time; Switching Waveforms
  • Page 18 – Hardware STORE Cycle; HSB To Output Active Time when write latch not set; Hardware STORE Pulse Width; Write Latch not set
  • Page 19 – Ordering Information; Part Numbering Nomenclature
  • Page 20 – Package Diagrams
  • Page 22 – Document History Page; Worldwide Sales and Design Support; Change
Loading the manual

PRELIMINARY

1 Mbit (128K x 8) Serial SPI nvSRAM

CY14B101Q1
CY14B101Q2
CY14B101Q3

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document #: 001-50091 Rev. *A

Revised February 2, 2009

Features

■

1 Mbit NonVolatile SRAM

❐

Internally organized as 128K x 8

❐

STORE

to QuantumTrap

®

nonvolatile elements initiated au-

tomatically on power down (AutoStore

®

) or by user using

HSB pin (Hardware Store) or SPI instruction (Software Store)

❐

RECALL

to SRAM initiated on power up (Power Up Recall

®

)

or by SPI Instruction (Software RECALL)

❐

Automatic STORE

on power down with a small capacitor

■

High Reliability

❐

Infinite Read, Write, and RECALLl cycles

❐

200,000 STORE

cycles to QuantumTrap

❐

Data Retention: 20 Years

■

High Speed Serial Peripheral Interface (SPI)

❐

40 MHz Clock rate

❐

Supports SPI Modes 0 (0,0) and 3 (1,1)

■

Write Protection

❐

Hardware Protection using Write Protect (WP) Pin

❐

Software Protection using Write Disable Instruction

❐

Software Block Protection for 1/4,1/2, or entire Array

■

Low Power Consumption

❐

Single 3V +20%, –10% operation

❐

Average Vcc current of 10 mA at 40 MHz operation

■

Industry Standard Configurations

❐

Commercial and industrial temperatures

❐

CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐

8-pin DFN and 16-pin SOIC Packages

❐

RoHS compliant

Functional Overview

The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3

combines a 1 Mbit nonvolatile static RAM with a nonvolatile

element in each memory cell. The memory is organized as 128K

words of 8 bits each. The embedded nonvolatile elements incor-

porate the QuantumTrap technology, creating the world’s most

reliable nonvolatile memory. The SRAM provides infinite read

and write cycles, while the QuantumTrap cell provides highly

reliable nonvolatile storage of data. Data transfers from SRAM to

the nonvolatile elements (STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

Both STORE and RECALL operations can also be triggered by

the user.

Instruction

register

Address
Decoder

Data I/O register

Status register

Power Control

STORE/RECALL

Control

Instruction decode

Write protect
Control logic

Quantum Trap

STORE

RECALL

SI

SCK

V

CC

V

CAP

SO

HSB

128K X 8

SRAM ARRAY

128K X 8

A0-A16

D0-D7

HOLD

CS

WP

Logic Block Diagram

[+] Feedback

"Loading the manual" means you need to wait until the file loads and becomes available for online reading. Some manuals are very large, and the time they take to appear depends on your internet speed.

Summary

Page 2 - PRELIMINARY; Pinouts; GND; GND

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 2 of 22 Pinouts Figure 1. Pin Diagram - 8-Pin DFN [1, 2, 3] Figure 2. Pin Diagram - 16-Pin SOIC Table 1. Pin Definitions Pin Name I/O Type Description CS Input Chip Select . Activates the device when pulled LOW. Driving th...

Page 3 - Device Operation; Table 2; SRAM Write; Table 2. Feature Summary; Feature

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 3 of 22 Device Operation CY14B101Q1/CY14B101Q2/CY14B101Q3 is 1 Mbit nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capabili...

Page 4 - Figure 3; Software Store Operation; Note; RECALL Operation

PRELIMINARY CY14B101Q1CY14B101Q2CY14B101Q3 Document #: 001-50091 Rev. *A Page 4 of 22 capacitor (V CAP ) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from V CC to charge the capacitor connected to th...

Other Cypress Models

All Cypress Other