Analog Devices AD9912 - Manual
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Table of Contents:
- Page 2 – TABLE OF CONTENTS; REVISION HISTORY
- Page 3 – SPECIFICATIONS; DC SPECIFICATIONS
- Page 5 – AC SPECIFICATIONS
- Page 7 – ABSOLUTE MAXIMUM RATINGS; Parameter; THERMAL RESISTANCE; is specified for the worst-case conditions, that is, a device; Table 4. Thermal Resistance; Unit; ESD CAUTION
- Page 8 – PIN CONFIGURATION AND FUNCTION DESCRIPTIONS; Table 5. Pin Function Descriptions
- Page 10 – TYPICAL PERFORMANCE CHARACTERISTICS; = 10 kΩ, unless otherwise noted. See Figure 26 for 1 GHz reference
- Page 15 – INPUT/OUTPUT TERMINATION RECOMMENDATIONS
- Page 16 – THEORY OF OPERATION; OVERVIEW; is
- Page 17 – FTW; phase; RECONSTRUCTION FILTER
- Page 18 – third
- Page 19 – SYSCLK INPUTS; Functional Description; SYSCLK PLL bypassed; SYSCLK PLL Doubler
- Page 20 – SYSCLK PLL Multiplier; Multiplier
- Page 21 – Primary 1.8 V Differential HSTL Driver; HARMONIC SPUR REDUCTION
- Page 23 – THERMAL PERFORMANCE; Table 7. Thermal Parameters; PD
- Page 24 – DEFAULT OUTPUT FREQUENCY ON POWER-UP; frequencies scale 1:1 with f; Status Pin
- Page 25 – POWER SUPPLY PARTITIONING; increases from 50 MHz to 400 MHz.
- Page 26 – SERIAL CONTROL PORT; SERIAL CONTROL PORT PIN DESCRIPTIONS; (serial data out) is used only in the unidirectional I/O mode; OPERATION OF SERIAL CONTROL PORT; Framing a Communication Cycle with CSB
- Page 27 – Read; The MSB of the instruction word is R/W; Table 9. Byte Transfer Count; Streaming mode; MSB/LSB FIRST TRANSFERS
- Page 30 – Reserved
- Page 32 – I/O REGISTER DESCRIPTIONS; Register 0x0000—Serial Port Configuration
- Page 34 – FREQUENCY TUNING WORD (REGISTER 0x01A0 TO REGISTER 0x01AD)
- Page 35 – Register 0x01AC—Phase; DDS phase word
- Page 36 – See the Harmonic Spur Reduction section.
- Page 38 – OUTLINE DIMENSIONS
- Page 39 – ORDERING GUIDE; Model; Evaluation Board
- Page 40 – NOTES
1 GSPS Direct Digital
Synthesizer with 14-Bit DAC
AD9912
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
FEATURES
1 GSPS internal clock speed (up to 400 MHz output directly)
Integrated 1 GSPS 14-bit DAC
48-bit frequency tuning word with 4 µHz resolution
Differential HSTL comparator
Flexible system clock input accepts either crystal or external
reference clock
On-chip low noise PLL REFCLK multiplier
2 SpurKiller channels
Low jitter clock doubler for frequencies up to 750 MHz
Single-ended CMOS comparator; frequencies of <150 MHz
Programmable output divider for CMOS output
Serial I/O control
Excellent dynamic performance
Software controlled power-down
Available in two 64-lead LFCSP packages
Residual phase noise @ 250 MHz
10 Hz offset: −113 dBc/Hz
1 kHz offset: −133 dBc/Hz
100 kHz offset: −153 dBc/Hz
40 MHz offset: −161 dBc/Hz
APPLICATIONS
Agile LO frequency synthesis
Low jitter, fine tune clock generation
Test and measurement equipment
Wireless base stations and controllers
Secure communications
Fast frequency hopping
GENERAL DESCRIPTION
The AD9912 is a direct digital synthesizer (DDS) that features
an integrated 14-bit digital-to-analog converter (DAC). The
AD9912 features a 48-bit frequency tuning word (FTW) that
can synthesize frequencies in step sizes no larger than 4 μHz.
Absolute frequency accuracy can be achieved by adjusting the
DAC system clock.
The AD9912 also features an integrated system clock phase-
locked loop (PLL) that allows for system clock inputs as low
as 25 MHz.
The AD9912 operates over an industrial temperature range,
spanning −40°C to +85°C.
BASIC BLOCK DIAGRAM
FDBK_IN
DAC_OUT
AD9912
S1 TO S4
OUT
OUT_CMOS
FILTER
SYSTEM CLOCK
MULTIPLIER
SERIAL PORT,
I/O LOGIC
CLOCK
OUTPUT
DRIVERS
DIGITAL
INTERFACE
06763-
001
DIRECT
DIGITAL
SYNTHESIS
CORE
STARTUP
CONFIGURATION
LOGIC
Figure 1.
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Summary
AD9912 Rev. D | Page 2 of 40 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description .......................
AD9912 Rev. D | Page 3 of 40 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVSS = 0 V, DVSS = 0 V, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD_I/O (Pin 1) 3.135 3.30 3.465...
AD9912 Rev. D | Page 5 of 40 AC SPECIFICATIONS f S = 1 GHz, DAC R SET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified in the DC Specifications section. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments FDBK_IN INPUT Pin 40, Pin 41 Input Frequency Range 10 400...
